Random number generation on Spartan-3E

Question

I need to generate pseudo-random numbers for my genetic algorithm on a Spartan-3E FPGA and i want to implement it in verilog: could you give me any pointers on this?

Answer 1

Typically you'd use the IEEE.math_real uniform function

use IEEE.math_real.all;
procedure UNIFORM (variable Seed1,Seed2:inout integer; variable X:out real);

But do a tiny bit a research on pseudo random number generators (PRNGs) and you'll find many variants that are simple LFSR's - which look remarkably similar to CRC generators.

Here are several resources if you want to roll your own starting from existing, working PRNGs:

http://www.opencores.org/?do=project&who=systemc_rng

http://verificationguild.com/modules.php?name=Downloads&d_op=viewdownload&cid=3

Here's a CRC VHDL code generator:

http://www.easics.be/webtools/crctool

Answer 2

Of course the random generator by Adam is not synthesizable! You have to explicitly create an LFSR. http://en.wikipedia.org/wiki/LFSR

Following example might help. It is an 8-bit maximal LFSR

module lfsr(input clk, reset, en, output reg [7:0] q);
  always @(posedge clk or posedge reset) begin
    if (reset)
      q <= 8'd1; // can be anything except zero
    else if (en)
      q <= {q[6:0], q[7] ^ q[5] ^ q[4] ^ q[3]}; // polynomial for maximal LFSR
  end
endmodule;

Answer 3

The pointer above to OpenCores has a file in the verilog folder called: rng.v

I have used it in a Spartan-3AN and it works great. My code used the random number generator to select a random PWM after I programmed the part and it covered all the selectable PWMs.

Answer 4

There is an online tool that can generate Verilog or VHDL code for a pseudo-random number generator. It's on OutputLogic.com

Answer 5

I agree with the LFSR. I have made one before and it is used for encryption.

Answer 6

You've already got some good answers, but I'll just point out the canonical guide to LFSRs in FPGAs is here:

http://www.xilinx.com/support/documentation/application%5Fnotes/xapp052.pdf

It's a bit Xilinx specific in places (which is OK for your FPGA :) but the principals are transferable to others.