Is there a TAP (Test Anything Protocol) implementation for Verilog? It would be nice because then I could use prove to check my results automatically.
Update: 10/9/09: It was asked why not use assertions. Partly TAP gives me some good reporting such as number of files and number of tests. It also can be used with smolder for reporting of progress over time.
10/12/09: I'm looking for a minimal implentation with number of tests at the beginning and end and the ok, diag and fail functions. is() would really nice, but not necessary.