Can't make sense of error in System Verilog

Question

I tried to compile code

module counter(
    input clk,
    input upSignal,
    input downSignal,
    output [7:0] count
   );
        always_ff @(posedge clk) begin
          if (upSignal)
              count <= count + 1;
          else if (downSignal)
              count <= count - 1;
        end
    endmodule

but I get the error

Error (10170): Verilog HDL syntax error at counter.v(7) near text "@"; expecting ".", or "("

what does it mean?

Answer 1

Hi Bo

Quartus does support some systemverilog. See this link for details > Quartus Help

For quartus to automatically recognise that you are using system verilog, you need to call your file something.sv

So in this case, probably counter.sv

If your file is called counter.v, then you will get an error. I can confirm that is does indeed compile with Quartus II v10.0.

I would recommend changing your module output port to reg, Quartus didn't complain, but a simulator would.

output reg [7:0] count

Let us know how you get on.

Cheers