Can we have an array of instances for a custom module. eg : we can have -> input [15:0] a; this creates a bus can we do same thing for custom modules -> DFF [15:0] d; where DFF = custom module . Here I intend to create 16 instances of the DFF module.. Thanks for any help in advance.... ...
Using pseudo code here. Are there pros and cons to these styles: Say you have an alu that can do add, and, or and xor. Is it better to have code that computes the possible answers all the time then select the answer based on the opcode (in this case a one hot): alu_add = a + b; alu_and = a & b; alu_or = a | b; alu_xor = a ^ b; ... ...
I'm trying to cheaply and accurately predict all the system-verilog dependencies for a build flow. It is ok to over-predict the dependencies and find a few verilog files that aren't sv dependencies, but I don't want to miss any dependencies. Do I actually have to parse the Verilog in order to determine all its dependencies? There are ...
Recently as I am working with the hardware design group developing an ASIC. And I am drawing a lot of timing diagrams for which I am using Microsoft EXCEL to draw them, as it is easy to import to word document. But, things are getting more and more difficult with EXCEL. My question? How do you guys draw timing diagrams? Is there any eas...
Is there a TAP (Test Anything Protocol) implementation for Verilog? It would be nice because then I could use prove to check my results automatically. Update: 10/9/09: It was asked why not use assertions. Partly TAP gives me some good reporting such as number of files and number of tests. It also can be used with smolder for reportin...
I have looked on the web and the discussions/examples appear to be for traditional software development. Since Verilog and VHDL (used for chip design, e.g. FPGAs and ASICs) are similar to software development C and C++ it would appear to make sense. However they have some differences being fundamentally parallel and requiring hardware ...
Is this allowed? input w; input [8:0]y; output reg [8:0]x; always@(w) begin //x[0] or A is never on in any next state assign x[0] = 0; assign x[1]= (y[0]&~w) | (y[5]&~w) | (y[6]&~w) | (y[7]&~w) | (y[8]&~w); //B assign x[2]= (y[1]&~w); //C assign x[3]= (y[2]&~w); //D assign x[4]= (...
So I have an array of 4 RAM modules that I want to be able to read/write to based on two different selector signals. Right now I'm instantiating the RAM using intermediary signals: genvar i; generate for (i = 0; i < regnum; i=i+1) begin: regs rfram_generic rf (clk,rst,ce_a_int[i],addr_a_int[i],do_a_int[i], ...
I have written two modules DLatch and RSLatch and i want to write verilog code to join those two to match the diagram here: ( http://img130.imageshack.us/i/mod.tif/ However i dont know how to go about doing this. ...
Hello, I've always kinda wanted to make my own microprocessor.. I've read http://stackoverflow.com/questions/632698/how-can-i-make-my-own-microcontroller . I tried multiple times to learn some Verilog and VHDL. But for the life of me I just can not get my head around the language styles. I come from a C/C++/C# background and have dabbed...
( insert really basic question disclaimer here ) More specifically, I have the following declaration: output reg icache_ram_rw And in some point of the code I need to put the zero value in this reg. Here's what I've tried and the outcomes: assign icache_ram_rw = 1'b0; ( declarative lvalue or port sink reg icache_ram_rw must be a wir...
I'm new to Verilog. Can someone suggest a learning resource, book, video, blog, anything that they had a good personal experience with and helped them learn it faster? If it helps, I have experience programming in several high-level languages, but have no experience programming in C. Thanks ...
I'm getting into microcontroller programming and have been hearing contrasting views. What language is most used in the industry for microcontroller programming? Is this what you use in your own work? If not, why not? P.S.: I'm hoping the answer is not assembly language. ...
How do I write a Verilog code that declares a 12-bit by 16-word memory called x? How do I write a Verilog code that assigns the fifth word of mem1 the decimal value 127 on the positive edge of the signal clock. I am not clear on what word here means in terms of verilog, can someone give an example. ...
I am having a hard time understanding the following syntax in verilog: input [15:0] a; // 16-bit input output [31:0] result; // 32-bit output assign result = {{16{a[15]}}, {a[15:0]}}; I know the assign statement will wire something up to the result bus using wires and combinational logic, but what's up with the curly braces and 16{a[...
If say I have the following wire set-ups, is the wire assignment all valid? wire[3:1] w; wire w1; wire [1:0] w2; A) w1 = w[2]; B) w2 = w[1:0]; C) w2 = w[1:2]; I am guessing that everything is valid.... ...
I don't know what is wrong with the code below, can someone help me debug module iloop(z,a); input [31:0] a; output z; reg [4:0] i; reg s, z; initial begin s = 0; for(i=0; i<32; i=i+1) s = s | a[i]; z = !s; end endmodule ...
what does the schematic looks like in the following verilog code? module mystery2(s, c, x, y, z); input x, y, z; output s, c; assign {c, s} = x + y + z; endmodule I know that {c, s} means that they are concatenated, what does this looks like in schematics? and x + y + z is just an add between the three input right and we have ...
I have a wire that is about 4 levels deep and I really don't want the hassle of having to propagate it up the hierarchy. Is there any way to assign the wire using some sort of referencing? I know I can access the wire by typing: cca.cpu0.cca3_cpu.nc1_cp_checkpoint but assign cca.cpu0.cca3_cpu.nc1_cp_checkpoint = checkpoint; doesn...
I am designing a chip using a verilog. I have a 3 bit counter.I want that when the counter is in its 8th loop , there should be a clock glitch and thereafter work normally.What could be the possible ways of producing a clock glitch in a verilog design? ...