xilinx

How to use an OLED display for an Avnet Virtex4?

I have an Avnet ADS-XLX-V4FX-EVL12-G (Virtex4 Evaluation Board) with OLED display. I used Xilinx EDK 10.1 with Xilinx Platform Studio 10.1 and succeded to upload some basic app to the board (serial communication). Now I would like to use the OLED display mounted on the board but I have no ideea how to begin. I found the uCLinux distro f...

Obsolete Xilinx Chip

My company is trying to build a pcb with an obsolete xilinx fpga (XC3042A) which is part of the XC3000 series chips. Does anyone have any experience programming the data to the chip? I'm looking for what software, hardware, etc. people have used. ...

Why is XST optimizing away my registers and how do I stop it?

I have a simple verilog program that increments a 32 bit counter, converts the number to an ASCII string using $sformat and then pushes the string to the host machine 1 byte at a time using an FTDI FT245RL. Unfortunately Xilinx XST keeps optimizing away the string register vector. I've tried mucking around with various initialization...

Flip-Flop triggered on the edge of two signals

I need a flip flop that reacts on the edges of two different signals. Something like this: if(rising_edge(sig1)) then bit <= '0'; elsif(rising_edge(sig2)) then bit <= '1'; end if; Does such a flip flop exist or is there some other technique i could use? I need this to be synthesizable on a Xilinx Virtex-5 FPGA. Thanks ...

VERILOG : Can we have an array of custom modules ??

Can we have an array of instances for a custom module. eg : we can have -> input [15:0] a; this creates a bus can we do same thing for custom modules -> DFF [15:0] d; where DFF = custom module . Here I intend to create 16 instances of the DFF module.. Thanks for any help in advance.... ...

Using XILINX XPS with Microblaze - quickest way to program the fpga

I'm designing a micro controller based around the microblaze microprocessor on a xilinx fpga. Most of the hardware setup is done. All I'm updating at this point is the c code to be run on the microblaze. Is there a way in XPS to not have to rebuild the entire project, just the c code portion. It takes around 20 minutes to rebuild the ent...

code breaks when trying to run any lwip function

I am trying to run the sample code for tftp server. I get no complaints when synthesizing my hardware or compiling the code. However, when I add the lwip_init() statement, it seems to stop working (it doesn't output any of the print statements). This is very frustrating and I have no idea what is causing it. Any ideas? Thanks #include <...

VHDL: how to set a value on an inout port?

I am trying to test a VHDL component, but can't seem to get this one inout port to give me any behaviour. I've tried setting the port to everything from '1' to '-', but it still comes up as 'U' in simulation. Any sugestions what might be wrong? ...

How do you run Xilinx91i in ubuntu?

I installed Xilinx91i on my comp under /usr/Xilinx91i/, but I don't know how to start it. Can someone help? ...

Xilinx Microblaze C and assembly

I have an application written in C for a Xilinx Microblaze core. However, the performance isn't quite what I want so I was considering rewriting some of the core functions in assembly. I'm having trouble figuring out how to get Xilinx Platform Studio to compile both into a single ELF file though. How can I do it? ...

Why IEEE vhdl standard library is not STL?

IEEE vhdl language reference manual only defined a limited set of standard packages.And it do not defined the functionalities on the standard types,such as STD_LOGIC.So there are no standard AND2, INV components/operator. It seems that Altera's MAX+Plus II do not support AND2, INV component(if there are,please feel free to correct me),b...

VHDL conditional generation from makefile

I have a vhdl design that needs adapting to different variants. It would be nice to be able to generate the configurations from a makefile. The makefile for the generation of one project is ready and working. I want to avoid having different very similar files for different projects. The only differences between the projects are a coupl...

How to synthesis verilog cores made in xilinx core generator?

I used coregen to develop a divider core. Here are the steps I tried to use that divider in my design (not sure if its quite correct): 1) copied wrapper (core_name.v), .ngc file, and .veo file into main design folder 2) instantiate the core in my main verilog module using the veo template: core_name u1(.a(a_p), .b(b_p), .c(c_p), .d(d_p);...

Verilog code simulates but does not run as predicted on FPGA

I did a behavioral simulation of my code, and it works perfectly. The results are as predicted. When I synthesize my code and upload it to a spartan 3e FPGA and try to analyze using chipscope, the results are not even close to what I would have expected. What have I done incorrectly? http://pastebin.com/XWMekL7r ...

How to define clock input in Xilinx

Hey, I have almost no experience with Xilinx. I have a group project for a Digital Logic course that is due soon, where my partner, who was supposed to take care of the Xilinx simulations decided to bail on me. So here I am trying to figure it out last minute. I have designed a synchronous counter using a few JK Flip Flops and I need to...

Configuration Management for FPGA Designs

Which configuration management tool is the best for FPGA designs, specifically Xilinx FPGA's programmed with VHDL and C for the embedded (microblaze) software? ...

Programming VHDL on Linux?

Hello, Anyone knows good enviroment to program VHDL and simulate it (don't matter Xilinx or Altera) using Linux? Thanks Br ...

ERROR:Simulator:222 in Xillinx ISE for Verilog

Hi, I came upon an error after the syntax check is SUCCESSFUL, ie. there is no error. However, I came upon an error during the simulation. The error does not make any sense at all. Please advise. What can be done? Thank you. ERROR:Simulator:222 - Generated C++ compilation was unsuccessful Codegen failed for module "t_MUX_device" ...

How commonly used are the xilinx chips?

I'm beginning to learn embedded with C (and maybe some C++) and someone from the office said they're willing to donate a free xilinx chip they've got sitting on their shelf. I was thinking more along the lines of an Arduino, especially that the Arduino tutorials and sample projects are abundant. Can someone confirm how xilinx chips co...

[VHDL] how much for Sound (ADC) reading in 24khz?

Hi there, how much "sound inputs" of high fidelify (128K 44kH) may be made via ordinary FPGA (Xilinx Spartan 3, what-so-ever) without using external ADC converters (only voltage-balanced input optically taken from audio jack)? Here, http://stackoverflow.com/questions/3165266/generating-a-pure-sine-wave-as-output-form-fpga-using-vhdl-cod...