IEEE vhdl language reference manual only defined a limited set of standard packages.And it do not defined the functionalities on the standard types,such as STD_LOGIC.So there are no standard AND2, INV components/operator.
It seems that Altera's MAX+Plus II do not support AND2, INV component(if there are,please feel free to correct me),but Xilinx Foundation does.
Why IEEE vhdl standard library could not become something like STL in the C++ world?
thanks.