views:

152

answers:

2

I have some VHDL code I'm writing for a class. However, the synthesis tool identifies cell3, cell2, and cell1 as "dead" code and it won't synthesize it.

I really have no idea what's going on to cause cell 3,2,1 to be removed in synthesis; I've reviewed it some 5+ times and asked several different people and I can't find the "why".

Not looking for a solution, just a pointer to why.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;



entity multiply is
    Port ( a : in  STD_LOGIC_VECTOR (3 downto 0);
           b : in  STD_LOGIC;
           clk : in  STD_LOGIC;
           rst : in  STD_LOGIC;

           p : out  STD_LOGIC);

end multiply;

architecture Behavioral of multiply is

    component cell_a port(
       s: in std_logic;
       c: in std_logic;
       a: in std_logic;
       b: in std_logic;
       clk: in std_logic;

       c_out: out std_logic;
       s_out: out std_logic);
    end component;

    signal c_s_0: std_logic; --loopback wire for cell 0 from carry to sum
    signal c_s_1: std_logic;
    signal c_s_2: std_logic;
    signal c_s_3: std_logic;

    signal xfer1_0: std_logic;  --wire between 1 and 0
    signal xfer2_1: std_logic;  --"  2 and 1
    signal xfer3_2: std_logic;  --"  3 and 2


begin

    cell3: cell_a port map(
            clk => clk, 
            s => c_s_3 , c => '0',   a => a(3), b => b,
            c_out => c_s_3, s_out => xfer3_2
            );

    cell2: cell_a port map(
            clk => clk, 
            s => c_s_2 , c => xfer3_2, a => a(2), b => b, 
            c_out => c_s_2, s_out => xfer2_1
            );

    cell1: cell_a port map(
            clk => clk, 
            s => c_s_1, c => xfer2_1, a => a(1), b => b, 
            c_out => c_s_1, s_out => xfer1_0
            );

    cell0: cell_a port map(
            clk => clk, 
            s => c_s_0 , c => xfer1_0, a => a(0), b => b, 
            c_out => c_s_0, s_out => p
            );
    process(clk)
    begin
     if(clk'event and clk = '1') then
      if(rst = '1') then
      --reset logic here. Magic happens and the circuit goes to all 0
      end if;
     end if;
    end process;
end Behavioral;
+1  A: 

It might be that cell1-3 are getting optimized out by the synthesis since the output of this block "p" is only 1 bit.

You don't need to fully evaluate all the logic to determine whether this bit should be a 0 or a 1.

DasBoot
Apparently you do, otherwise it wouldn't have been written. As I said in my answer, it is more likely an error in cell_a's architecture.
Zooba
I don't understand your comment. I can write something that isn't needed and that logic will be optimized out by the synthesis tool. For example if I write out = in | !in, then the synthesis tool will optimize out the OR gate and the INV gate, and just write out = 1.
DasBoot
Yes, but if you meant for it to be included and it isn't, it is more likely an error on your part. The question implies that the developer wants all the code to be used, and the fact that it isn't being used is incorrect.
Zooba
DasBoot, I was wanting the cells to actually *do* something. That was the problem. :)
Paul Nathan
OK. Glad you solved your issue.
DasBoot
+6  A: 

All I can suggest without seeing the rest of the code is that your 'c' input to cell_a is unused, which causes all the outputs from cell3/2/1 to be unused (hence, dead code, since it produces no observable results).

cell0 instantiates because multiplier's 'p' output is observable.

Zooba
Thank you. If I had thought of that, I'd have been done hours ago. Thank you.
Paul Nathan