I have some VHDL code I'm writing for a class. However, the synthesis tool identifies cell3, cell2, and cell1 as "dead" code and it won't synthesize it.
I really have no idea what's going on to cause cell 3,2,1 to be removed in synthesis; I've reviewed it some 5+ times and asked several different people and I can't find the "why".
Not looking for a solution, just a pointer to why.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity multiply is
Port ( a : in STD_LOGIC_VECTOR (3 downto 0);
b : in STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC;
p : out STD_LOGIC);
end multiply;
architecture Behavioral of multiply is
component cell_a port(
s: in std_logic;
c: in std_logic;
a: in std_logic;
b: in std_logic;
clk: in std_logic;
c_out: out std_logic;
s_out: out std_logic);
end component;
signal c_s_0: std_logic; --loopback wire for cell 0 from carry to sum
signal c_s_1: std_logic;
signal c_s_2: std_logic;
signal c_s_3: std_logic;
signal xfer1_0: std_logic; --wire between 1 and 0
signal xfer2_1: std_logic; --" 2 and 1
signal xfer3_2: std_logic; --" 3 and 2
begin
cell3: cell_a port map(
clk => clk,
s => c_s_3 , c => '0', a => a(3), b => b,
c_out => c_s_3, s_out => xfer3_2
);
cell2: cell_a port map(
clk => clk,
s => c_s_2 , c => xfer3_2, a => a(2), b => b,
c_out => c_s_2, s_out => xfer2_1
);
cell1: cell_a port map(
clk => clk,
s => c_s_1, c => xfer2_1, a => a(1), b => b,
c_out => c_s_1, s_out => xfer1_0
);
cell0: cell_a port map(
clk => clk,
s => c_s_0 , c => xfer1_0, a => a(0), b => b,
c_out => c_s_0, s_out => p
);
process(clk)
begin
if(clk'event and clk = '1') then
if(rst = '1') then
--reset logic here. Magic happens and the circuit goes to all 0
end if;
end if;
end process;
end Behavioral;