Hi,
How do you concatenate bits in VHDL? I'm trying to use the following code:
Case b0 & b1 & b2 & b3 is ...
and it throws an error
Thanks
Hi,
How do you concatenate bits in VHDL? I'm trying to use the following code:
Case b0 & b1 & b2 & b3 is ...
and it throws an error
Thanks
The concatenation operator '&' is allowed on the right side of the signal assignment operator '<=', only
You are not allowed to use the concatenation operator with the case statement. One possible solution is to use a variable within the process:
process(b0,b1,b2,b3)
variable bcat : std_logic_vector(0 to 3);
begin
bcat := b0 & b1 & b2 & b3;
case bcat is
when "0000" => x <= 1;
when others => x <= 2;
end case;
end process;