altera

How does a TABLE work in AHDL?

I have an implementation of a Control Unit (UC) in AHDL, and I'm supposed to simulate it and see if it works as defined in the correspondent ASM diagram. I used MAX+plus II to simulate it, and it doesn't work as I expected, but I can't really say what's wrong because I am not familiar with AHDL, let alone the TABLE part. Here is my Cont...

Why IEEE vhdl standard library is not STL?

IEEE vhdl language reference manual only defined a limited set of standard packages.And it do not defined the functionalities on the standard types,such as STD_LOGIC.So there are no standard AND2, INV components/operator. It seems that Altera's MAX+Plus II do not support AND2, INV component(if there are,please feel free to correct me),b...

Should you remove all warnings in your Verilog or VHDL design? Why or why not?

In (regular) software I have worked at companies where the gcc option -Wall is used to show all warnings. Then they need to be dealt with. With non-trivial FPGA/ASIC design in Verilog or VHDL there are often many many warnings. Should I worry about all of them? Do you have any specific techniques to suggest? My flow is mainly for FP...

Need help for this syntax: "#define LEDs (char *) 0x0003010"

I'm doing programming of a softcore processor, Nios II from Altera, below is the code in one of the tutorial, I manage to get the code working by testing it on the hardware (DE2 board), however, I could not understand the code. #define Switches (volatile char *) 0x0003000 #define LEDs (char *) 0x0003010 void main() { while (1) *LEDs = *...

Programming VHDL on Linux?

Hello, Anyone knows good enviroment to program VHDL and simulate it (don't matter Xilinx or Altera) using Linux? Thanks Br ...

Complex floating-point sequential logic in Verilog

Hi, I'm trying to write a synthesizable 3D rasterizer in Verilog/SystemVerilog. The rasterizer right now is not really a 3D rasterizer: it just receives six 32-bits floats for vertex position (vertA_pos_x, vertA_pos_y, vertB_pos_x, vertB_pos_y, vertC_pos_x, vertC_pos_y) and nine 8-bits integers for vertex coloring (vertA_color_r, vertA_...

Reset an Altera M9K's content to 0 (power-up value)

Good day, I am working on a Stratix III FPGA which contains M9K block memories, the contents of which are conveniently initialised to zero on power-on. This suits my application very well. Is there a way to reset the contents back to zero without power-cycling/reflashing/etc the FPGA? There seems to be no such option in the megawizard ...

I can't open project I closed in Quatrus in windows 7

I can't open project I closed in Quatrus in windows 7 and this message always appear " Can't open project -- you do not have permission to write to all the files or create new files in the projects database directory. " what should I do ...