I'm relatively new to VHDL. I'm attempting to write code to do unsigned multiplication using a combination of full adders. When compiling it passes up to the port mapping. I've resolved the errors in the first map, but all of the others give me problems.
I get the same error for each: "Expression actuals in port map aspect must be static"
Here's my code. Any help is appreciated. In addition, if you have general tips based on looking at my code I would be thankful.
Thanks, Buzkie
library ieee;
use ieee.std_logic_1164.all;
entity fulladder is
port (a, b, c: in std_logic;
sout, cout: out std_logic);
end fulladder;
architecture behav of fulladder is
begin
sout <= (a xor b) xor c ;
cout <= (a and b) or (c and (a xor b));
end behav;
library ieee;
use ieee.std_logic_1164.all;
entity unsignedmult is
port (a,b: in std_logic_vector (3 downto 0);
pro: out std_logic_vector (7 downto 0));
end unsignedmult;
architecture synth of unsignedmult is
--Declarations
signal c1,c2,c3,c4,c5: std_logic_vector (3 downto 0);
signal s1,s2,s3,s4: std_logic_vector (2 downto 0);
component fulladder
port (a,b,c:in std_logic;
sout,cout:out std_logic);
end component;
begin
--Row 0 ----Sin-----A&B-------Cin--Sout---Cout
Fand00: fulladder port map('0',(a(0) and b(0)),'0',pro(0),c1(0));
Fand01: fulladder port map('0',(a(1) and b(0)),'0',s1(0),c1(1));
Fand02: fulladder port map('0',(a(2) and b(0)),'0',s1(1),c1(2));
Fand03: fulladder port map('0',(a(3) and b(0)),'0',s1(2),c1(3));
--Row 1
Fand10: fulladder port map(s1(0),(a(0) and b(1)),c1(0),pro(1),c2(0));
Fand11: fulladder port map(s1(1),(a(1) and b(1)),c1(1),s2(0),c2(1));
Fand12: fulladder port map(s1(2),(a(2) and b(1)),c1(2),s2(1),c2(2));
Fand13: fulladder port map('0',(a(3) and b(1)),c1(3),s2(2),c2(3));
--Row 2
Fand20: fulladder
----Sin------A&B------Cin-Sout-Cout
port map(s2(0),(a(0) and b(2)),c2(0),pro(2),c3(0));
Fand21: fulladder
----Sin--A&B------Cin-Sout-Cout
port map(s2(1),(a(1) and b(2)),c2(1),s3(0),c3(1));
Fand22: fulladder
----Sin--A&B------Cin-Sout-Cout
port map(s2(2),(a(2) and b(2)),c2(2),s3(1),c3(2));
Fand23: fulladder
----Sin--A&B------Cin-Sout-Cout
port map('0',(a(3) and b(2)),c2(3),s3(2),c3(3));
--Row 3
Fand30: fulladder
----Sin------A&B------Cin-Sout-Cout
port map(s3(0),(a(0) and b(3)),c3(0),pro(3),c4(0));
Fand31: fulladder
----Sin--A&B------Cin-Sout-Cout
port map(s3(1),(a(1) and b(3)),c3(1),s4(0),c4(1));
Fand32: fulladder
----Sin--A&B------Cin-Sout-Cout
port map(s3(2),(a(2) and b(3)),c3(2),s4(1),c4(2));
Fand33: fulladder
----Sin--A&B------Cin-Sout-Cout
port map('0',(a(3) and b(3)),c3(3),s4(2),c4(3));
--Row 4
F40: fulladder
port map(s4(0),c4(0),'0',pro(4),c5(0));
F41: fulladder
port map(s4(1),c4(1),c5(0),pro(5),c5(1));
F42: fulladder
port map(s4(2),c4(2),c5(1),pro(6),c5(2));
F43: fulladder
port map('0',c4(3),c5(2),pro(7),c5(3));
end synth;