hdl

Where should I begin with HDLs?

I am a self-taught embedded developer. I mostly use AVRs programmed in C and ASM, but I have dabbled with other systems. I am looking to move onto more complex devices like CPLDs and FPGAs, but I have no idea where to start. So my one and a half questions are: Do you prefer VHDL or Verilog and why? What is a good way for one with no pr...

How do I convert a number to two's complement in verilog?

I am trying to design a 4-bit adder subtracter in verilog. This is only the second thing I have ever written in verilog, and I don't know all the correct syntax yet. This is the module I have so far: module Question3(carryin, X, Y, Z, S, carryout, overflow); parameter n = 4; input carryin, Z; input [n-1:0]X, Y; output re...

What are the best practices for Hardware Description Languages (Verilog, VHDL etc.)

What best practices should be observed when implementing HDL code? What are the commonalities and differences when compared to more common software development fields? ...

Can dynamically pluggable modules be done in VHDL?

In c (embedded) a plugin can be implemented by defining a function pointer table and an address range that the module can be loaded into. This requires linker directive to allocate the space and define the location of the function table. Is there a similar mechanism in HDL / VHDL or Verilog. I guess what I am thinking is to define a b...

Problem setting output flags for ALU in "Nand to Tetris" course

Although I tagged this homework, it is actually for a course which I am doing on my own for free. Anyway, the course is called "From Nand to Tetris" and I'm hoping someone here has seen or taken the course so I can get some help. I am at the stage where I am building the ALU with the supplied hdl language. My problem is that I can't get ...

Assigning wires deep in a nested set of modules

I have a wire that is about 4 levels deep and I really don't want the hassle of having to propagate it up the hierarchy. Is there any way to assign the wire using some sort of referencing? I know I can access the wire by typing: cca.cpu0.cca3_cpu.nc1_cp_checkpoint but assign cca.cpu0.cca3_cpu.nc1_cp_checkpoint = checkpoint; doesn...

How to synthesis verilog cores made in xilinx core generator?

I used coregen to develop a divider core. Here are the steps I tried to use that divider in my design (not sure if its quite correct): 1) copied wrapper (core_name.v), .ngc file, and .veo file into main design folder 2) instantiate the core in my main verilog module using the veo template: core_name u1(.a(a_p), .b(b_p), .c(c_p), .d(d_p);...

Verilog code simulates but does not run as predicted on FPGA

I did a behavioral simulation of my code, and it works perfectly. The results are as predicted. When I synthesize my code and upload it to a spartan 3e FPGA and try to analyze using chipscope, the results are not even close to what I would have expected. What have I done incorrectly? http://pastebin.com/XWMekL7r ...

Can Verilog testbenches work with a real clock?

I wrote a counter in Verilog, and then a testbench to test it. My testbench gives the correct results, so my code is OK. But is it gives the result of a long time instantly. Is it possible to take the result with real time. I mean in every one second my testbench will produce a new line of result?? (and if it is possible how?) ...

In Specman, why is my macro label for the code body returning garbage?

Similar to this post http://feedproxy.google.com/~r/cadence/community/blogs/fv/~3/IvdCIla8_Es/extending-multiple-when-subtypes-simultaneously.aspx I want to make a macro that does loop unrolling to get around some of the when-subtyping and inheritance issues Specman has. I've started with: -- macros.e <' define <FOREACH_UNROLL'action...