alu

Problem setting output flags for ALU in "Nand to Tetris" course

Although I tagged this homework, it is actually for a course which I am doing on my own for free. Anyway, the course is called "From Nand to Tetris" and I'm hoping someone here has seen or taken the course so I can get some help. I am at the stage where I am building the ALU with the supplied hdl language. My problem is that I can't get ...

Making a 4-bit ALU from several 1-bit ALUs in VHDL

Hey, I'm trying to combine several 1 bit ALUs into a 4 bit ALU. I am confused about how to actually do this in VHDL. Here is the code for the 1bit ALU that I am using: component alu1 -- define the 1 bit alu component port(a, b: std_logic_vector(1 downto 0); m: in std_logic_vector(1 downto 0); result: out std_logic_vector(1 downto ...