VHDL conditional generation from makefile

Question

I have a vhdl design that needs adapting to different variants. It would be nice to be able to generate the configurations from a makefile. The makefile for the generation of one project is ready and working.

I want to avoid having different very similar files for different projects. The only differences between the projects are a couple of rows somewhere, and that one of them includes a bunch of vhdl files (and components) that the other one does not need.

I want to avoid having two different top level vhd files, for example. Instead I want to use conditionals inside the top file in order to include (or not) the other vhdl files and components, depending on project.

Do you have any suggestion as to how to do this?

I have tried to use an external pre-compiler (gcc's) but could not make it work. Furthermore I don't really want to force other developers to install gcc, or the vhdl files not to be usable from within the Xilinx IDE.

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Edit: Adding an example

I have two products, A and B. I want to use the same files for both products, with conditionals to exclude some parts for product B, generate the configurations for different HW parts, and surely other things.

I want to generate the configs from the command line with: make product_A, and make product_B.

If I put generates in my vhdl to include/exclude code depending on the target, then xst needs to know what target is being built. The question is about how to pass the current target from the makefile to xst.

In C code compiling with gcc, I'd put in the source code:

#if defined(product_B)
    ...
#elsif defined(product_A)
    ...
#endif

, then set the define in the makefile:

product_A: source.c
    gcc -Dproduct_A source.c

product_B: source.c
    gcc -Dproduct_B source.c

Answer 1

You have a couple of options here:

1. Try not to have different files, but implement all the different versions in a single one. This is by far the most robust approach. VHDL has some useful constructs to help you with this: generics, generate statements, packages, configurations and so on.
2. Use an external macro pre-processor to have VHDL file "templates". Some hardened Unixoids use the venerable m4 tool. I would take a different path and use a full-fledged programming language like Python with some templating library. Then, you can easily incorporate the generation of real VHDL files from these templates in your makefiles.

By all means, try going with option (1) first. The differences may not be as bad as you think.

Answer 2

Have you considered using the vhdl GENERATE statement and wrapping it around the logic you want to be configurable.

name : FOR N IN 1 TO 8 GENERATE

  concurrent statements here

END GENERATE name;

Then if you add some configuration generics to the top level file you can control how the generates run.

EDIT

You can set GENERICS from the command line in XST using:

-generics {name=value name=value}

Support for this was only added from 9.1 onwards.

Answer 3

Generate is the way to do it - to have something compiled in or not, you need an if generate:

product_a_gen: if product_a='1' generate
    -- some code in here
end generate product_a_gen;
product_b_gen: if product_b='1' generate
    -- some code in here
end generate product_b_gen;

VHDL2008 adds extensions to generate, so you can have case and else parts. Doulos have an appnote on this.

Take care with XST and passing in generics, they are limited on which types are supported.