schematic from verilog code

Question

what does the schematic looks like in the following verilog code?

  module mystery2(s, c, x, y, z);
  input x, y, z;
  output s, c;
  assign {c, s} = x + y + z;
endmodule

I know that {c, s} means that they are concatenated, what does this looks like in schematics? and x + y + z is just an add between the three input right and we have one wire coming out of it

Answer 1

You can think of x + y + z as the sum of 3 1-bit wires, but the sum requires 2 bits. Thus, I would consider {c,s} as 2 1-bit wires "coming out".

The answer to your main question depends on how the circuit is implemented. There are many possible schematic representations for your code because you have described a digital logic function at a high level of abstraction.

Run that code through your synthesis tool and see what kind of a gate-level netlist is produced. Then look at it in a schematic viewer. Let the tools do the work for you.

Answer 2

Ha this guy is in my class, and this is part of a diagnostic put together by the prof. to determine if you are ready for the class or not. I'm guessing he's not...