verilog

Passing a 256-bit wire to a C function through the Verilog VPI

I have a 256-bit value in Verilog: reg [255:0] val; I want to define a system task $foo that calls out to external C using the VPI, so I can call $foo like this: $foo(val); Now, in the C definition for the function 'foo', I cannot simply read the argument as an integer (PLI_INT32), because I have too many bits to fit in one of thos...

verilog modelsim fpga

Sorry for Newbish question. I am trying to learn about FPGA programming. Before I spend $1K on a FPGA board: if I just want to learn Verilog, can I run it entirely in Modelsim? (I realize there are some timing issues that only show up in actual chips; but for learning syntax / style of coding / ...)_ Thanks! ...

Using Verilog Parameter keyword

I am using the parameter keyword to define a state ie RESET = 5'b00000. If I want to use $display to printout the state name instead of the binary representation, or display the state name in my simulation wave viewer, how can I do this? It doesn't work to try to print it out as a string (as you would expect), so I'm wondering if this ...

Are you allowed to have a module identifier be the same as the module type in Verilog?

For example module top debouncer debouncer(...); endmodule module debouncer ... endmodule Can I instantiate a debouncer as "debouncer" in the top module, or is that illegal? ...

Syntax for using an array of wires as input

I have the following module: module add_8bit ( output wire co, output wire [7:0] r, input wire ci, input wire [7:0] x, input wire [7:0] y ); I am trying to use it via the following code: wire rbit [7:0]; wire onebit [7:0]; wire twocomp [7:0]; wire tco, tci; add_8bit t9 (...

How to NOT use while() loops in verilog (for synthesis)?

I've gotten in the habit of developing a lot testbenches and use for() and while() loops for testing purpose. Thats fine. The problem is that I've taken this habit over to coding for circuits which should be synthesizable. XST and others refuse to synthesize code (without additional modification to synthesis parameters) such as: while (...

count leading zero in single cycle datapath

As you all might know that the MIPS instruction set supports clz (count leading zero) as follows: clz $t0,$t1 count leading zeros t0 = # of leading zeros in t1 I am writing a single cycle datapath in verilog and was just wondering what the ALU needs to support in order for me to do this... any ideas?? ...

Load half word and load byte in a single cycle datapath

There was this problem that has been asked about implementing a load byte into a single cycle datapath without having to change the data memory, and the solution was something below. This is actually quite a realistic question; most memory systems are entirely word-based, and individual bytes are typically only dealt with i...

How to synthesis verilog cores made in xilinx core generator?

I used coregen to develop a divider core. Here are the steps I tried to use that divider in my design (not sure if its quite correct): 1) copied wrapper (core_name.v), .ngc file, and .veo file into main design folder 2) instantiate the core in my main verilog module using the veo template: core_name u1(.a(a_p), .b(b_p), .c(c_p), .d(d_p);...

What's the difference between $stop and $finish in Verilog?

I'm using a GUI simulator, and they both seem to do the same thing. ...

Verilog code simulates but does not run as predicted on FPGA

I did a behavioral simulation of my code, and it works perfectly. The results are as predicted. When I synthesize my code and upload it to a spartan 3e FPGA and try to analyze using chipscope, the results are not even close to what I would have expected. What have I done incorrectly? http://pastebin.com/XWMekL7r ...

Where can I get Verilog codings?

I am doing a project in Verilog, and the project is a low power parallel multiplier. I am going to fed the codings in FPGA kit. I need model Veriog codings. In which site can I get or suggest some good books. ...

Assign a value to a reg in Verilog

for (j=0;j<k;j=j+1) begin:loop2 assign row[i+1][j][m+i:0] = {1'b0,row[i][j][m+i-1:0]}; end row is a register. It does not work as I am doing it. Can anyone please help me to fix it? Thank you very much. ...

Using Regular Expressions for Verilog Port Mapping

I have a really long port map where I want to replace a bunch of SignalName[i], with .SignalName(SignalName[i]), I think I can do this easily with regular expressions, but I can't for the life of me figure out how. Any ideas? ...

Global declarations are illegal in Verilog 2001 syntax!

I have written something small in verilog: `define LW 6'b100011 `define SW 6'b101011 parameter [3:0] i_fetch = 4'b0001, decode_rr = 4'b0010, mem_addr = 4'b0100, alu_exec = 4'b1000; and i am getting this error: Error: test.v(5): (vlog-2155) Global declarations are illegal in Verilog 2001 syntax. What I am doing wrong...

AES BYTE SYSTOLIC ARCHITECTURE.

we are implementing AES BYTE SYSTOLIC ARCHITECTURE. CODE:- module key_expansion(kld,clk,key,key_expand,en); input kld; // flag when high initializes the key expansion module input clk; input en; //enable signal is set high when we want our new key to be assigned on output port input [127:0] key; //input key wire [31:0] w0,w1,w2...

How do I get rid of sensitivity list warning when synthesizing Verilog code?

I am getting the warning that: One or more signals are missing in the sensitivity list of always block. always@(Address)begin ReadData = instructMem[Address]; end How do I get rid of this warning? ...

How can I rewrite Verilog code to remove extra reg?

How can I rewrite the code below so that I don't need to have an extra reg mul. I just wanted to take the 32 bits of the resulting 32 * 32 bit multiplication and put it into Result input signed[31:0] Reg1; input signed[31:0] Reg2; output[31:0] Result; reg signed[31:0] Result; reg[63:0] mul; mul = Reg1 * Reg2; Result = mul[31:0]; ...

Should you remove all warnings in your Verilog or VHDL design? Why or why not?

In (regular) software I have worked at companies where the gcc option -Wall is used to show all warnings. Then they need to be dealt with. With non-trivial FPGA/ASIC design in Verilog or VHDL there are often many many warnings. Should I worry about all of them? Do you have any specific techniques to suggest? My flow is mainly for FP...

how to store data in ram in verilog

`// this is stimulus file module final_stim; reg [7:0] in,in_data; reg clk,rst_n,rd,wr,rd_data,wr_data; wire [7:0] out,out_wr; wire[7:0] d; integer i; reg kld,f; reg [127:0]key; wire [127:0] key_expand; wire [7:0]out_data; reg [7:0] k; //wire [7:0] k1,k2,k3,k4,k5,k6,k7,k8,k9,k10,k11,k12,k13,k14,k15,k16; wire [7:0] out_...