we are implementing AES BYTE SYSTOLIC ARCHITECTURE.
CODE:-
module key_expansion(kld,clk,key,key_expand,en);
input kld; // flag when high initializes the key expansion module
input clk;
input en; //enable signal is set high when we want our new key to be assigned on output port
input [127:0] key; //input key
wire [31:0] w0,w1,w2,w3;
output [127:0] key_expand;
reg[127:0] key_expand;
reg [31:0] w[3:0];
reg [3:0] ctr; //counter in order to make the key generation after every 16 cycles
wire [31:0] c0,c1,c2,c3;
wire [31:0] tmp_w;
wire [31:0] subword;
wire [31:0] rcon;
assign w0 = w[0];
assign w1 = w[1];
assign w2 = w[2];
assign w3 = w[3];
//always @(posedge clk)
always @(posedge clk)
begin
w[0] <= #1 kld ? key[127:096] : w[0]^subword^rcon; //subword comes from a module that byte substitutes the word according to our logic.the module for rcon is also attached as under
end
always @(posedge clk)
begin
w[1] <= #1 kld ? key[095:064] : w[0]^w[1]^subword^rcon;
end
always @(posedge clk)
begin
w[2] <= #1 kld ? key[063:032] : w[0]^w[2]^w[1]^subword^rcon;
end
always @(posedge clk)
begin
w[3] <= #1 kld ? key[031:000] : w[0]^w[3]^w[2]^w[1]^subword^rcon;
end
assign tmp_w = w[3];
aes_sbox u0( .a(tmp_w[23:16]), .d(subword[31:24])); // aes-sbox is a kind of ROM containing byte substituted values of the input given to it
aes_sbox u1( .a(tmp_w[15:08]), .d(subword[23:16]));
aes_sbox u2( .a(tmp_w[07:00]), .d(subword[15:08]));
aes_sbox u3( .a(tmp_w[31:24]), .d(subword[07:00]));
aes_rcon r0( .clk(clk), .kld(kld), .out_rcon(rcon));
always@(posedge clk)
begin
if (!en) // when enable is high initialize the ctr
begin
ctr<=0;
end
else if (|ctr) // if ctr is non zero we dont want to output our key
begin
key_expand<=0;
ctr<=(ctr+1)%16; ///increment ctr till 16
end
else if (!(|ctr)) // if ctr is zero
begin
key_expand<={w0,w1,w2,w3}; output the wires on output port by concatenating them
ctr<=(ctr+1)%16;
end
end
endmodule
/////////////////////////////////////////RCON/////////////////////////////////////
module aes_rcon(clk, kld, out_rcon);
input clk;
input kld;
output [31:0] out_rcon;
reg [31:0] out_rcon;
reg [3:0] rcnt;
wire [3:0] rcnt_next;
always @(posedge clk)
if(kld) out_rcon <= #1 32'h01_00_00_00;
else out_rcon <= #1 frcon(rcnt_next);
assign rcnt_next = rcnt + 4'h1;
always @(posedge clk)
if(kld) rcnt <= #1 4'h0;
else rcnt <= #1 rcnt_next;
function [31:0] frcon;
input [3:0] i;
case(i) // synopsys parallel_case
4'h0: frcon=32'h01_00_00_00;
4'h1: frcon=32'h02_00_00_00;
4'h2: frcon=32'h04_00_00_00;
4'h3: frcon=32'h08_00_00_00;
4'h4: frcon=32'h10_00_00_00;
4'h5: frcon=32'h20_00_00_00;
4'h6: frcon=32'h40_00_00_00;
4'h7: frcon=32'h80_00_00_00;
4'h8: frcon=32'h1b_00_00_00;
4'h9: frcon=32'h36_00_00_00;
default: frcon=32'h00_00_00_00;
endcase
endfunction
endmodule
problem:verilog code has been attached
This is a basic aes round key generation code.We need to generate 11 keys,first the cipher
key and then ten round keys according to our logic specified.This code works perfectly well
for us when we want to generate a new key at every posedge of clk but we need to modify it
in order to generate each roundkey after a delay of 16 cycles......keeping in mind that we are generating posedge of clock after evry 20 time units.
how to go about it?how to stop aes from generataing keys at every posedge.We came up with this counter and enable theory but it doesnot seem to work properly.PLZ HELP.THANX