How can I rewrite Verilog code to remove extra reg?

Question

How can I rewrite the code below so that I don't need to have an extra reg mul. I just wanted to take the 32 bits of the resulting 32 * 32 bit multiplication and put it into Result

input signed[31:0] Reg1; 
input signed[31:0] Reg2; 
output[31:0] Result; 
reg signed[31:0] Result; 
reg[63:0] mul; 
mul = Reg1 * Reg2; 
Result = mul[31:0];

Answer 1

What about:

Result = (Reg1 * Reg2)[31:0];