What's the difference between $stop and $finish in Verilog?

Question

I'm using a GUI simulator, and they both seem to do the same thing.

Answer 1

Hi

This link explains it to some extent.

$stop - When Verilog encounters a $stop, it pauses as if you sent a Ctrl-C.

$finish - Verilog exits as if you sent Ctrl-D when it encounters $finish.

Taken from Page 15 of this indtroduction PDF.

cheers

Answer 2

$finish exits the simulation and gives control back to the operating system.

$stop suspends the simulation and puts the simulator in an interactive mode.

Answer 3

A quick reference link:

$finish;
    Finishes a simulation and exits the simulation process.
$stop;
    Halts a simulation and enters an interactive debug mode.

Answer 4

According to the IEEE Standard for Verilog (1364-2005, Section 17.4, "Simulation control system tasks"), $stop should suspend the simulation, and $finish should make the simulator exit and pass control back to the host operating system. Of course, different simulators may implement the specification in subtlely different ways, and not all simulators are 100% compliant with the spec.

The documentation for your simulator might provide a more detailed description of its behavior, especially with respect to GUI vs. command-line modes.