verilog

output not updating until next clock cycle

I have the code module below always @(posedge Clk) begin ForwardA = 0; ForwardB = 0; //EX Hazard if (EXMEMRegWrite == 1) begin if (EXMEMrd != 0) if (EXMEMrd == IDEXrs) ForwardA = 2'b10; if (EXMEMrd == IDEXrt && IDEXTest == 0) ForwardB = 2'b10; end //MEM Hazard if (MEMWBRegWrite == 1) begin if (MEMWBrd != 0)...

converting if else statement to ternary

I have translated the following code using ternary. However, I knew there was something wrong with it. Can someone please point me into the right direction? ForwardA = 0; ForwardB = 0; //EX Hazard if (EXMEMRegWrite == 1) begin if (EXMEMrd != 0) if (EXMEMrd == IDEXrs) ForwardA = 2'b10; if (EXMEMrd == IDEXrt && IDEXTest =...

binary number comparison

If I have a 32 bit two's complement number and I want to know what is the easiest way to know of two numbers are equal... what would be the fastest bitwise operator to know this? I know xor'ing both numbers and check if the results are zero works well... any other one's? how about if a number is greater than 0?? I can check the 31'st bi...

How to declare and use 1D and 2D byte arrays in Verilog?

How to declare and use 1D and 2D byte arrays in Verilog? eg. how to do something like byte a_2D[3][3]; byte a_1D[3]; // using 1D for (int i=0; i< 3; i++) { a_1D[i] = (byte)i; } // using 2D for (int i=0; i< 3; i++) { for (int j=0; j< 3; j++) { a_2D[i][j] = (byte)i*j; } } ...

ERROR:Simulator:222 in Xillinx ISE for Verilog

Hi, I came upon an error after the syntax check is SUCCESSFUL, ie. there is no error. However, I came upon an error during the simulation. The error does not make any sense at all. Please advise. What can be done? Thank you. ERROR:Simulator:222 - Generated C++ compilation was unsuccessful Codegen failed for module "t_MUX_device" ...

Can Verilog testbenches work with a real clock?

I wrote a counter in Verilog, and then a testbench to test it. My testbench gives the correct results, so my code is OK. But is it gives the result of a long time instantly. Is it possible to take the result with real time. I mean in every one second my testbench will produce a new line of result?? (and if it is possible how?) ...

VHDL/Verilog related programming forums?

Hardware design with VHDL or Verilog is more like programming nowadays. But, I see SO members are not so actively talking about VHDL/Verilog programming. Is there any forum dealing with hardware design with Verilog/VHDL/SystemVerilog or SystemC? ...

Complex floating-point sequential logic in Verilog

Hi, I'm trying to write a synthesizable 3D rasterizer in Verilog/SystemVerilog. The rasterizer right now is not really a 3D rasterizer: it just receives six 32-bits floats for vertex position (vertA_pos_x, vertA_pos_y, vertB_pos_x, vertB_pos_y, vertC_pos_x, vertC_pos_y) and nine 8-bits integers for vertex coloring (vertA_color_r, vertA_...

Does Verilog support short circuit evaluation?

If I have an if statement like: if(risingEdge && cnt == 3'b111) begin ... end Will it check on cnt if risingEdge is not true? Does this even matter inside of an HDL? ...

Why does the chip control the language to choose

I've asked the question before what language should I learn for embedded development. Most embedded engineers said c and c++ are a must, but also pointed out that it depends on the chip. Can someone clarify? Is it a compiler issue or what? Do chips come with their own specific compilers (like a c compiler or c++ compiler) and that's wh...

Import Code from FPGA Board (Spartan 3E)

Is there any way to import code from an already programmed FPGA board, in this case, it is a Spartan 3E board. That is to say, verilog code has already been uploaded to it, so I would like a way to receive the code back in the computer since I have lost the copy. I uploaded the code with Xilinx ISE, but am not sure if it is possible to g...

What does this Verilogger Pro error mean?

I got an error while programming in Verilogger Pro: error: maximum allowable lines in evaluation version exceeded What does this mean? ...

How do I code a basic flip flop in Verilog Pro?

I tried to code a basic flip flop using NAND gates in Verilog Pro, but the waveform I'm getting is not correct. Please see what's wrong with it. //design module module rstt(s,r,q,qbar); input r,s; output q,qbar; nand n1(q,r,qbar); nand n2(qbar,s,q); endmodule //stimulus module module test; reg r,s; wire q,qbar; initial begin r=1'b1; s...

Basic Verilog question: shift register

I am very new to HDL language. I have a question about how to program a shift register. (i know i shift to the other direction). Why does the book use wire[N-1:0] r_next? what's drawback of my implementation? thanks my first try is as following module lesson04#(parameter N=8)( input wire clk, reset, input wire data, output...

DCM in Xilinx 10.1

How can I generate different clocks in DCM? Suppose I want 20mhz, 24mhz, 28mhz, 32mhz, clocks simultaneously using single digital clock manager ip core in xilinx 10.1. ...

Sharing constants across languages

I have a long list of constants that I need access to in several projects which are in different languages(Verilog, C, C++ and C#). Rather than repeating them in each language, is there a good way to share these? The only thing I could think of would be a text file and a preprocessing script? Is this the best solution or is there somet...

modelsim source code

The following is some modelsim code: begin tb_in_top = 0; #5 tb_in_top = 4'b0000;#5 tb_in_top = 4'b0001; #5 tb_in_top = 4'b0010;#5 tb_in_top = 4'b0011; #5 tb_in_top = 4'b0100;#5 tb_in_top = 4'b0101; #5 tb_in_top = 4'b0110;#5 tb_in_top = 4'b0111; #5 tb_in_top = 4'b1000;#5 tb_in_top = 4'b1001; #5 tb_in_top = 4...

Handling parameterization in SystemVerilog packages

SystemVerilog added packages to provide namespaces for common code pieces (functions, types, constants, etc). But since packages are not instantiated, they cannot be parameterized, so dealing with parameterized members is problematic. In practice I have found this pretty limiting since very often my custom types have some parameters di...

For Loops in Verilog

I have problems with this Verilog code. Basically, it won't let me do the Y = 3'di statement. Basically, I want Y to equal i. I am pretty sure the problem is the i. So, is there a way to do this in Verilog? Also, W is an input with 8 bits (in other words, W[7:0]). for (i = 7; i >= 0; i = i - 1) begin if(W[i]) Y=3'di; end Thanks. ...

Reset an Altera M9K's content to 0 (power-up value)

Good day, I am working on a Stratix III FPGA which contains M9K block memories, the contents of which are conveniently initialised to zero on power-on. This suits my application very well. Is there a way to reset the contents back to zero without power-cycling/reflashing/etc the FPGA? There seems to be no such option in the megawizard ...