How do I code a basic flip flop in Verilog Pro?

Question

I tried to code a basic flip flop using NAND gates in Verilog Pro, but the waveform I'm getting is not correct. Please see what's wrong with it.

//design module
module rstt(s,r,q,qbar);
input r,s;
output q,qbar;
nand n1(q,r,qbar);
nand n2(qbar,s,q);
endmodule

//stimulus module 
module test;
reg r,s;
wire q,qbar;
initial begin
r=1'b1;
s=1'b0;
#25 r=1'b0;
  s=1'b1;
#25 r=1'b1;
  s=1'b1;
#100 $finish;
end
endmodule

Answer 1

You did not instantiate your rstt module inside your test module. This means that the wires (q and qbar) inside module test are undriven. That is why they remain as straight lines instead of toggling. According to the IEEE Verilog standard, a undriven wire will default to 1'bz.

Try something like this:

//design module
module rstt(s,r,q,qbar);
input r,s;
output q,qbar;
nand n1(q,r,qbar);
nand n2(qbar,s,q);
endmodule

//stimulus module 
module test;
reg r,s;
wire q,qbar;

rstt i0 (
    .s    (s),
    .r    (r),
    .q    (q),
    .qbar (qbar)
);

initial begin
r=1'b1;
s=1'b0;
#25 r=1'b0;
  s=1'b1;
#25 r=1'b1;
  s=1'b1;
#100 $finish;
end
endmodule

Note that your problem is not specific to any simulator.