verilog basic questions

Question

1. How do I write a Verilog code that declares a 12-bit by 16-word memory called x?
2. How do I write a Verilog code that assigns the fifth word of mem1 the decimal value 127 on the positive edge of the signal clock.

I am not clear on what word here means in terms of verilog, can someone give an example.

Answer 1

A plain 12-bit vector named v:

reg [11:0] v;

A 12-bit by 16-word memory named x:

reg [11:0] x [0:15];

You can number them however you want, but a common convention is to number bits downward to 0 and words upward from 0, as above. In this case the memory contains 16 words:

x[0]
x[1]
...
x[15]

Each of the above memory words is declared to be 12 bits wide:

x[0][11]  (most significant bit of first word)
x[0][10]
...
x[0][0]   (least significant bit of first word)

A memory is a reg with one or more unpacked array dimensions (a range to the right of the variable name in the declaration), and a memory word is an array element of a memory with all unpacked dimensions specified. So x is a memory, x[0] is a memory word, and x[0][0] is a bit. Also, v is a vector and v[0] is a bit.

This assigns the fifth word of x on every positive edge of clock:

always @(posedge clock) x[4] = 127;