tags:

views:

45

answers:

1
Q: 

How do I implement a synthesizable DPLL in Verilog?

Is there any straight forward way to implement an all digital phase lock in synthesizable Verilog? Everything (including the VCO) should be synthesized. The signals I'm looking to lock to are ~0.1-1% of the system clock frequency. I am using one that I've reconstructed from 1980's IEEE papers, but it doesn't behave as well as advertised.

For simplicity, the lock can work on a binary pulse signal.

+1  A: 

In FPGA designs I normally use the built in DCMs, or PLLs.

The Cyclone 2 has up to 4 PLLs built in.

Have a look at PLLs in Cyclone 2.

George  2010-10-27 10:03:15
The built in PLL's are fine for clock synchronization and synthesis (I'm using one to get my 200MHz system clock from the 10MHz clock source). But they are extremely limited. They have enormous jitter for any kind of DSP purposes (they are designed to synchronize not de-jitter), they are also not very flexible being completely defined at synthesis time, and most importantly, the minimum frequency that the onboard PLL's can lock is about 10 MHz, about 10 times higher than my signal frequency.
crasic  2010-10-27 10:12:59
Yes, if you are trying to lock to a slow clock, the on board devices won't be much use. You could check [OpenCores](http://opencores.org/) for sample code.
George  2010-10-27 11:02:56

related questions

TAP (Test Anything Protocol) module for Verilog or SystemVerilog
Tool for drawing timing diagrams
finding all dependencies in a verilog compile
compute results and mux or not
VERILOG : Can we have an array of custom modules ??
Why is XST optimizing away my registers and how do I stop it?
Random number generation on Spartan-3E
task in verilog
Exporting tasks to 'C using DPI
FPGA based RTL evaluation
verilog or systemc for testbench
Is there a Perl tutorial for Verilog engineers?
$readmemh $writememh related resources
How would you implement this digital logic in Verilog or VHDL?
Finding the next in round-robin scheduling by bit twiddling
Can dynamically pluggable modules be done in VHDL?
Microcontroller + Verilog/VHDL simulator?
What are the best practices for Hardware Description Languages (Verilog, VHDL etc.)
How do I convert a number to two's complement in verilog?
Where should I begin with HDLs?
Whats the BEST way to setup a library to support links into precompiled Software for multiple platforms, compilation options.
How to write a linter?
Passing hierarchy into a Verilog module
Efficient synthesis of a 4-to-1 function in Verilog
Verilog automatic task