I need a flip flop that reacts on the edges of two different signals. Something like this: if(rising_edge(sig1)) then bit <= '0'; elsif(rising_edge(sig2)) then bit <= '1'; end if; Does such a flip flop exist or is there some other technique i could use? I need this to be synthesizable on a Xilinx Virtex-5 FPGA. Thanks ...
Using pseudo code here. Are there pros and cons to these styles: Say you have an alu that can do add, and, or and xor. Is it better to have code that computes the possible answers all the time then select the answer based on the opcode (in this case a one hot): alu_add = a + b; alu_and = a & b; alu_or = a | b; alu_xor = a ^ b; ... ...
I am trying to test a VHDL component, but can't seem to get this one inout port to give me any behaviour. I've tried setting the port to everything from '1' to '-', but it still comes up as 'U' in simulation. Any sugestions what might be wrong? ...
Are there any good, existing software tools available to assist in generating C header files with appropriate #defines for register offsets as well as bit definitions from VHDL? If any such tools do exist, what restrictions to they place on the VHDL and how are things that should be exported designated? So far, I've found these tools b...
I've got douta : in std_logic_vector (3 downto 0); doutb : in std_logic_vector (3 downto 0); c0 : in std_logic; f1 : in std_logic; f0 : in std_logic; res : out std_logic_vector (3 downto 0); Im' trying to build a simple ALU, and one of the function this ALU provide is when f1 and f0 both = 1 res = douta plus b plus c0 so ...
I am working on a 4 x 4 bit multiplier and am getting this error message, "Error (10500): VHDL syntax error at lab_6.vhd(33) near text "after"; expecting ")", or ","" twenty times. The problem is I have a ")" or a "," after the after statement. Here is the code: library ieee; use ieee.std_logic_1164.all; entity lab_6 is port(x, y...
I'm implementing whole set of 8051 instructions in VHDL from scratch. Most of things went well but stumbled on these 2 instructions: JB bit,rel 00100000 bit_address rel_address CJNE A,#data,rel 10110100 immediate_data rel_address Any help or hint is greatly appreciated. Thank you in advance! ...
I have looked on the web and the discussions/examples appear to be for traditional software development. Since Verilog and VHDL (used for chip design, e.g. FPGAs and ASICs) are similar to software development C and C++ it would appear to make sense. However they have some differences being fundamentally parallel and requiring hardware ...
I have an implementation of a Control Unit (UC) in AHDL, and I'm supposed to simulate it and see if it works as defined in the correspondent ASM diagram. I used MAX+plus II to simulate it, and it doesn't work as I expected, but I can't really say what's wrong because I am not familiar with AHDL, let alone the TABLE part. Here is my Cont...
Hi folks, I'm currently writing a 32Bit ALU (Add/Sub) in VHDL. I've got a problem with the overflow bit. I can't see when to set the overflow depending on the operation (addition, subtraction) and the input values. Can you help me ? best regards, Andre ...
What programming language has short and beautiful grammars (in EBNF)? Some languages are easer to be parsed. Some time ago I have created a simple VHDL parser, but it was very slow. Not because it is implemented completely in Python, but because VHDL grammar (in EBNF) is huge. The EBNF of Python is beautiful but it is not very short. I...
Hello, I've always kinda wanted to make my own microprocessor.. I've read http://stackoverflow.com/questions/632698/how-can-i-make-my-own-microcontroller . I tried multiple times to learn some Verilog and VHDL. But for the life of me I just can not get my head around the language styles. I come from a C/C++/C# background and have dabbed...
How do I send data represented by a binary string (e.g. "01011101000100111", length is variable) to an std_logic signal given either fixed delay or clock signal? I want this for a testbench so I'd want to be able to arbitrarily change the binary string with as little hassle as possible, so I'm thinking of using generate. ...
Hi ! Consider : process(a) According to the text i have : A process is first entered at the time of simulation, at which time it is executed until it suspends itself due to a wait statement or a sensitivity list. Am i right in inferring that a process WILL have to run once even without any events on the sensitivity list?...
How can I read data from rom_type? entity my_rom is port( addr: in std_logic_vector(3 downto 0); data: out std_logic_vector(0 to 7) ); end my_rom; architecture a of my_rom is type rom_type is array (0 to 7) of std_logic_vector(0 to 7); constant R1_ROM: rom_type := ( -- data ); begin data <= R1_rom(conv_integer(addr)); end ...
Hi, i'm coding a 4-bit binary adder with accumulator: library ieee; use ieee.std_logic_1164.all; entity binadder is port(n,clk,sh:in bit; x,y:inout std_logic_vector(3 downto 0); co:inout bit; done:out bit); end binadder; architecture binadder of binadder is signal state: integer range 0 to 3; signal sum,cin:...
Greetings everyone. I am designing a digital clock in VHDL which I am supposed to synthesize on a FPGA . I am cascading S1,S2,M1,M2,H1 and H2 where (S1 = second 1, M1 = Minute 1, H1 = hour 1 etc.). One of the requirements is for the clock to switch between 24HR display to a 12HR display format. How do I do it given that H1 and H2 are r...
I am planning to design a hardware simulation language like VHDL for my final year project. How should I go about it ? Any help would be greatly appreciated. ...
IEEE vhdl language reference manual only defined a limited set of standard packages.And it do not defined the functionalities on the standard types,such as STD_LOGIC.So there are no standard AND2, INV components/operator. It seems that Altera's MAX+Plus II do not support AND2, INV component(if there are,please feel free to correct me),b...
I have a vhdl design that needs adapting to different variants. It would be nice to be able to generate the configurations from a makefile. The makefile for the generation of one project is ready and working. I want to avoid having different very similar files for different projects. The only differences between the projects are a coupl...