Building a VHDL Clone

Question

I am planning to design a hardware simulation language like VHDL for my final year project. How should I go about it ?

Any help would be greatly appreciated.

Answer 1

Designing a language is as easy as designing a spec. Do you plan on designing a synthesizer and a simulator to go with it?

Answer 2

Have you been given this project or is one you have decided to do yourself ? If its the latter then you might want to rethink it I'm afraid. Big open opened projects like this don't always end well for the student sadly.

That said if you really want to do it then use VHDL yourself and read up on users comments on it. From that you will find out what annoys or irritates its users and then design something better.

Answer 3

If you want to design a hardware simulation language, start with the hardware.

Determine the level at which you want to simulate the hardware - transistor level, switch level, register level, behavioural level and what nots. Everything else starts from there. Once that is decided, you will know what constructs your language needs to support.

You will need to know what kind of devices your language can work with - transistors, gates, registers, muxes, memory, arithmetic units and what nots. Then, you need to find the appropriate models for each device.

In the end, you will definitely want to limit your scope. Limit yourself to doing one thing. The VHDL language was not invented by a single person in a day.

Answer 4

If you're looking for more examples of concurrent languages, there is MyHDL, and the XMOS XC which are other attempts away from the traditional Verilog and VHDL.