Error 10500, makes no sense.

Question

I am working on a 4 x 4 bit multiplier and am getting this error message, "Error (10500): VHDL syntax error at lab_6.vhd(33) near text "after"; expecting ")", or ","" twenty times. The problem is I have a ")" or a "," after the after statement. Here is the code:

library ieee;
use ieee.std_logic_1164.all;

entity lab_6 is
 port(x, y :in std_logic_vector(0 to 3);
   f :out std_logic_vector(0 to 7));
end lab_6;

architecture lab_6_arch of lab_6 is
signal sigand0, sigand1, sigand2, sigand3, sigand4, sigand5, sigand6, sigand7, sigand8, sigand9, sigand10, sigand11, sigand12, sigand13, sigand14, sigand15: std_logic;
signal sigha0, sigha1, sigha2, sigha3, sigha4, sigha5, sigha6, sigha7: std_logic;
signal sigfa0, sigfa1, sigfa2, sigfa3, sigfa4, sigfa5, sigfa6, sigfa7, sigfa8, sigfa9, sigfa10, sigfa11, sigfa12, sigfa13, sigfa14, sigfa15: std_logic;
component fa is
 port( x : in std_logic_vector(0 to 2);
    f : out std_logic_vector(0 to 1));
end component;

component a_n_d is
 port( x : in std_logic_vector (0 to 1);
  f : out std_logic);
end component;

component ha is
 port(x :in std_logic_vector(0 to 1);
   f :out std_logic_vector(0 to 1));
end component;

begin

module1: a_n_d
 port map( x(0) => x(0),
   y(0) => x(1),
   f => sigand0 after 3 ns);
f(0)<= sigand0;

module2_1: a_n_d
 port map( x(1) => x(0),
   y(0) => x(1),
   f => sigand1 after 3 ns);
module2_2: a_n_d
 port map( x(0) => x(0),
   y(1) => x(1),
   f => sigand2 after 3 ns);
module2_3:ha
 port map( sigand1 => x(0),
   sigand2 => x(1),
   f(0)=> sigha0 after 4 ns,
   f(1)=> sigha1 after 4 ns);
f(1)<=sigha0;

module3_1: a_n_d
 port map( x(2) => x(0),
   y(0) => x(1),
   f => sigand3 after 3 ns);
module3_2: a_n_d
 port map( x(1) => x(0),
   y(1) => x(1),
   f => sigand4 after 3 ns);
module3_3: a_n_d
  port map( x(0) => x(0),
   y(2) => x(1),
   f => sigand5 after 3 ns);
module3_4:fa
 port map( sigand3 => x(0),
   sigand4=> x(1),
   sigha1=>x(2),
   f(0)=> sigfa0 after 8 ns,
   f(1)=> sigfa1 after 8 ns);
module3_5:ha
 port map( sigfa0 => x(0),
   sigand5=> x(1),
   f(0)=> sigha2 after 4 ns,
   f(1)=> sigha3 after 4 ns);
f(2) <= sigha2;

module4_1: a_n_d
 port map( x(3) => x(0),
   y(0) => x(1),
   f => sigand6 after 3 ns);
module4_2: a_n_d
 port map( x(2) => x(0),
   y(1) => x(1),
   f => sigand7 after 3 ns);
module4_3: a_n_d
 port map( x(1) => x(0),
   y(2) => x(1),
   f => sigand8 after 3 ns);
module4_4: a_n_d
 port map( x(0) => x(0),
   y(3) => x(1),
   f => sigand9 after 3 ns);
module4_5:fa
 port map( sigand6 => x(0),
   sigand7=> x(1),
   sigfa1=>x(2),
   f(0)=> sigfa2 after 8 ns,
   f(1)=> sigfa3 after 8 ns);
module4_6:fa
 port map( sigand8 => x(0),
   sigfa2=> x(1),
   sigha3=>x(2),
   f(0)=> sigfa4 after 8 ns,
   f(1)=> sigfa5 after 8 ns);
module4_7:ha
 port map( sigfa4 => x(0),
   sigand5=> x(1),
   f(0)=> sigha4 after 4 ns,
   f(1)=> sigha5 after 4 ns);
f(3)<=sigha4;

module5_1: a_n_d
 port map( x(3) => x(0),
   y(1) => x(1),
   f => sigand10 after 3 ns);
module5_2: a_n_d
 port map( x(2) => x(0),
   y(2) => x(1),
   f => sigand11 after 3 ns);
module5_3: a_n_d
 port map( x(1) => x(0),
   y(3) => x(1),
    f => sigand12 after 3 ns);

module5_4:ha
 port map( sigfa3 => x(0),
   sigand10=> x(1),
    f(0)=> sigha6 after 4 ns,
    f(1)=> sigha7 after 4 ns);

module5_5:fa
 port map( sigand11 => x(0),
   sigha6=> x(1),
    sigfa5=>x(2),
   f(0)=> sigfa6 after 8 ns,
   f(1)=> sigfa7 after 8 ns);
module5_6:fa
 port map( sigand12 => x(0),
   sigfa6=> x(1),
   sigha5=>x(2),
   f(0)=> sigfa8 after 8 ns,
  f(1)=> sigfa9 after 8 ns);
f(4)<=sigfa8;

module6_1: a_n_d
 port map( x(3) => x(0),
   y(2) => x(1),
   f => sigand13 after 3 ns);
module6_2: a_n_d
 port map( x(2) => x(0),
   y(3) => x(1),
   f => sigand14 after 3 ns);
module6_3:fa
 port map( sigand13 => x(0),
   sigha7=> x(1),
   sigfa7=>x(2),
   f(0)=> sigfa10 after 8 ns,
   f(1)=> sigfa11 after 8 ns);
module6_4:fa
 port map( sigand14 => x(0),
   sigfa9=> x(1),
   sigfa10=>x(2),
   f(0)=> sigfa12 after 8 ns,
    f(1)=> sigfa13 after 8 ns);
 f(5)<=sigfa12;

 module7_1: a_n_d
  port map( x(3) => x(0),
    y(3) => x(1),
    f => sigand15 after 3 ns);
 module7_2:fa
  port map( sigand15 => x(0),
    sigfa11=> x(1),
    sigfa13=>x(2),
   f(0)=> sigfa14 after 8 ns,
   f(1)=> sigfa15 after 8 ns);
 f(6)<=sigfa14;
 f(7)<=sigfa15;
 end lab_6_arch;

I appreciate your help and time.

Answer 1

(Note: I don't know VHDL, I'm just going by what I found in the Qualis VHDL Quick Reference Card.)

Line 33 appears to be here:

module2_1: a_n_d
 port map( x(1) => x(0),
   y(0) => x(1),
   f => sigand1 after 3 ns);     <-- line 33

It appears that the after clause can only appear in statements with <=, not =>. The error you're getting essentially means that the compiler didn't expect to see after at that point, and instead showed you what it was expecting (which usually isn't terribly helpful).

Answer 2

Hi Adam,

you can't use any statements within a port map, port maps are only used to bind ports to signals (or ports of the enclosing hierarchy):

<component_identifier>: <component_name>
port map(
    <port_name> => <assigned_signal>,
    ...
)

What you can do instead is delaying the assignment of sigand0 to f(0):

module1: a_n_d
    port map( x(0) => x(0),
              y(0) => x(1),
              f => sigand0);

f(0) <= sigand0 after 3 ns;

Hope that helps!