How do I send data represented by a binary string (e.g. "01011101000100111"
, length is variable) to an std_logic signal given either fixed delay or clock signal? I want this for a testbench so I'd want to be able to arbitrarily change the binary string with as little hassle as possible, so I'm thinking of using generate
.
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230answers:
2
+2
A:
I humbly present a fixed-delay version (it is testbench code after all...). I've checked this and it works, but I'm more comfortable in verilog so this code may no be the nicest VHDL ever...
--
-- Clocking out bitstream
--
library ieee;
use ieee.std_logic_1164.all;
entity stackoverflow_strings is
end stackoverflow_strings;
-- this is testbench code, so we can use "wait"s inside a "for" loop.
architecture rtl of stackoverflow_strings is
signal my_output : std_ulogic;
begin
shift_data : process is
constant my_bits : std_logic_vector := B"100101010000100010101";
begin
my_output <= '0';
wait for 10 ns;
for i in my_bits'range loop
my_output <= my_bits(i);
wait for 10 ns;
end loop;
wait;
end process shift_data;
end rtl;
Marty
2009-11-27 18:48:38
That's actually nicely done, esp. if you're more Veriloggy :) Pedantic niggle - I'd change the architetcure name from RTL though - it clearly isn't an RTL description!
Martin Thompson
2009-12-02 11:59:22
A:
To add to Marty's fine answer:
To make it clocked, change the wait for 10 ns;
s to wait until rising_edge(clk);
Martin Thompson
2009-12-02 12:00:08