Changing time mode in a Digital Clock from 12HR to 24HR in VHDL

Question

Greetings everyone.

I am designing a digital clock in VHDL which I am supposed to synthesize on a FPGA . I am cascading S1,S2,M1,M2,H1 and H2 where (S1 = second 1, M1 = Minute 1, H1 = hour 1 etc.). One of the requirements is for the clock to switch between 24HR display to a 12HR display format. How do I do it given that H1 and H2 are represented by 4 bits each i.e. 8 bits in total to display the current hour. Will I need to concatenate HR1 and HR2 and then subtract 12 and then de-concatenate it again? keep in mind that X mod 12 is not a synthesizable operation for implementation in FPGA.

Thank you very much.

Answer 1

Basically you are doing all your arithmetic in binary coded decimal (BCD). So just build yourself a BCD comparator/subtractor:

if h1 = 1 and h2 > 2
  subtract 1 off h1
  subtract 2 off h2
  if h2 wrapped
     subtract 1 off h1

No mod required!