There are 3 stages involved in running a VHDL simulation. These are elaboration, initialisation and simulation.
At the beginning of the initialisation phase, the current time is set to 0. The simulation kernel then places all of the simulation processes in the active processes queue. Each simulation process is then taken from this queue and executed until it suspends. The order of execution of simuation processes during initialisation is not important. The initial execution of each simulation process ensures that all initial transactions are scheduled so that the simulation can continue.
A simulation process is suspended either implicity or explicity. A process with a sensitivity list is suspended implicity after its sequential statements have been executed to the end of the process. A process with one or more wait statements is suspended explicitly when its first wait statement is executed.
When the active processes queue is empty, the initialisation phase is complete.
So to answer your question, all processes will run once during the initialisation phase.