vhdl

Load half word and load byte in a single cycle datapath

There was this problem that has been asked about implementing a load byte into a single cycle datapath without having to change the data memory, and the solution was something below. This is actually quite a realistic question; most memory systems are entirely word-based, and individual bytes are typically only dealt with i...

[vhdl] 'if' vs 'when' for making multiplexer

i have been told to use 'when' statement to make multiplexer but not use 'if' statement as it will cause timing errors... i don't understand this ... so what is the difference between 'if' and 'when' ? and do they map to the same thing in hardware ? ...

Hardware representation for arrays in VHDL

Using VHDL i want to have a some registers that store 16 bit in each one. So i found that VHDL have a built in array,and i want to use it to store 16 bit in each element in iy so i want to know if VHDL map this array to actual registers or not? ...

Case statements in VHDL

Hi, When programming in VHDL, can you use a variable in a case statement? This variable will modified by one of the cases i.e. case task is when 1 => when 2 => when number => is this OK? ...

Starting work on a Pre-existing Project

So this is more of a generic question. I seem to keep finding myself being put on larger and larger projects. Recently I have been assigned to a very large project written in C and VHDL. The goal is for me to become familiar with the code and eventually take the lead on the project. This is by far the largest project I have been assi...

Should you remove all warnings in your Verilog or VHDL design? Why or why not?

In (regular) software I have worked at companies where the gcc option -Wall is used to show all warnings. Then they need to be dealt with. With non-trivial FPGA/ASIC design in Verilog or VHDL there are often many many warnings. Should I worry about all of them? Do you have any specific techniques to suggest? My flow is mainly for FP...

How to define clock input in Xilinx

Hey, I have almost no experience with Xilinx. I have a group project for a Digital Logic course that is due soon, where my partner, who was supposed to take care of the Xilinx simulations decided to bail on me. So here I am trying to figure it out last minute. I have designed a synchronous counter using a few JK Flip Flops and I need to...

Better ways to implement a modulo operation (algorithm question)

I've been trying to implement a modular exponentiator recently. I'm writing the code in VHDL, but I'm looking for advice of a more algorithmic nature. The main component of the modular exponentiator is a modular multiplier which I also have to implement myself. I haven't had any problems with the multiplication algorithm- it's just ad...

division by 2 in Binary Signed digit (Redundant Binary representation)

How can I do division by 2 in Binary Signed digit (Redundant Binary representation) ? Shifting won't work right ? ...

VHDL, using arithmetic & variables in "downto"?

Hey, Quick VHDL question, I don't have access to Xilinx at the moment due to dead laptop, so can't test this. I was wondering if it's possible to use variables and arithmetic in 'downto' statements, e.g: proc: process (x) begin y <= z(x downto 0) & z(7 downto x); end process; Thanks. ...

Comparison in Redundant binary representation RBR

How can I compare two numbers in the form of Redundant binary representation RBR ? Any Idea ? ...

include floating point library in vhdl

I have pex_pkg.vhd and I want to use this library to make floating point adder but altera max+plus II give me an error can't open "PEX_lib" how to include this library in max+plus ? ...

or_reduce functionality

what is the functionality of "or_reduce" function in VHDL ? ...

Professionnal VHDL IDE ?

Hello, Is there a good IDE to work with VHDL projects ? Or are most of the professionals working with emacs/vim/notepad++ ? ...

Large Scale VHDL modularization techniques

I'm thinking about implimenting a 16 bit CPU in VHDL. A simplish CPU. ADD, MULS, NEG, BitShift, JUMP, Relitive Jump, BREQ, Relitive BREQ, i don't know somethign along these lines> Probably all only working with 16bit operands. I might even cut it down and use only a single operand and a accumulator. With Some status regitsters, Carry, Ze...

Configuration Management for FPGA Designs

Which configuration management tool is the best for FPGA designs, specifically Xilinx FPGA's programmed with VHDL and C for the embedded (microblaze) software? ...

Signals and Variables in VHDL (order) - Problem

I have a signal and this signal is a bitvector (Z). The length of the bitvector depends on an input n, it is not fixed. In order to find the length, I have to do some computations. Can I define a signal after defining the variables ? It is giving me errors when I do that. It is working fine If I keep the signal before the variables (that...

Programming VHDL on Linux?

Hello, Anyone knows good enviroment to program VHDL and simulate it (don't matter Xilinx or Altera) using Linux? Thanks Br ...

VHDL/Verilog related programming forums?

Hardware design with VHDL or Verilog is more like programming nowadays. But, I see SO members are not so actively talking about VHDL/Verilog programming. Is there any forum dealing with hardware design with Verilog/VHDL/SystemVerilog or SystemC? ...

Generating a pure sine wave as output form FPGA using VHDL code

We know that the output of an FPGA is digital but can we genrate a pure analog sine wave using a vhdl code. also can I specify the frequency of the sine wav. ...