VHDL, using arithmetic & variables in "downto"?

Question

Hey,

Quick VHDL question, I don't have access to Xilinx at the moment due to dead laptop, so can't test this.

I was wondering if it's possible to use variables and arithmetic in 'downto' statements, e.g:

proc: process (x)
begin
  y <= z(x downto 0) & z(7 downto x);
end process;

Thanks.

Answer 1

Yes, for reference look this page. Arrays allow integer expressions as a definition of the endpoints of a range.

Answer 2

I wouldn't bet that it was synthesisable without trying it though :)

Answer 3

My guess is that it would synthesize to a large and ugly multiplexer instead of a simple shift register which is looks like you are trying to create.