Signals and Variables in VHDL (order) - Problem

Question

I have a signal and this signal is a bitvector (Z). The length of the bitvector depends on an input n, it is not fixed. In order to find the length, I have to do some computations. Can I define a signal after defining the variables ? It is giving me errors when I do that. It is working fine If I keep the signal before the variables (that what is showing below) .. but I don't want that .. the length of Z depends on the computations of the variables. What is the solution ?

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;


entity BSD_Full_Comp is
        Generic (n:integer:=8);
        Port(X, Y : inout  std_logic_vector(n-1 downto 0);
             FZ : out std_logic_vector(1 downto 0));
end BSD_Full_Comp;

architecture struct of BSD_Full_Comp is


Component BSD_BitComparator
    Port ( Ai_1  : inout  STD_LOGIC; Ai_0  : inout  STD_LOGIC;
           Bi_1  : inout  STD_LOGIC; Bi_0  : inout  STD_LOGIC;
           S1 : out  STD_LOGIC; S0 : out  STD_LOGIC
      );
END Component;



Signal Z : std_logic_vector(2*n-3 downto 0);



begin

    ass : process

Variable length : integer := n;
Variable pow : integer :=0 ;
Variable ZS : integer :=0;
begin
while length /= 0 loop
length := length/2;
pow := pow+1;
end loop;
length := 2 ** pow;
ZS := length - n;

wait;

    end process;



end struct;

Answer 1

Looks like you're trying to change the size of a hardware bus depending on the result of calculation? Remember that once you compile the circuit and burn it on to the FGPA, all your bus sizes are fixed. It's possible to have an FPGA change it's configuration on the fly, but I'd guess that it's not necessary a lot of the time. And I'd guess that it's tricky to do, too.

Maybe explain what exactly you are trying to calculate, and maybe we can come up with a different way of doing it.

A few other things. I'm not 100% familiar with VHDL, but do you need the bi-directional ports (the inouts)? Also, you don't seem to be using BSD_BitComparator; or ports X, Y or FZ; or signal Z in your architecture description.

Answer 2

The length of the bitvector depends on an input n, it is not fixed.

It is fixed, it's a generic. Once you've compiled and elaborated (ie built) the FPGA, n is fixed. And that's fine, you can use that to define the lengths of signals within the architecture.

As with the other respondent, I'm not sure what you're trying to do with your process. Are you trying to calculate the length that the Z signal will need to be?

If so, you can put it in a function, and use the function in the declaration of Z:

signal Z:std_logic_vector(calc_z_high_bit(n) downto 0);

Answer 3

A generic is fixed at compile/elaboration time. A variable can change during runtime. So, what you are aiming for isn't directly possible they way you are trying to do it.

If you want to dynamically specify some bitslice of the bus, you would need to define the bus to be the biggest it can be, and then use your computed n to mux out the slice of the bus you need.