Best way to approach FPGA Device Requirements

Question

When designing FPGA systems how can I estimate roughly the number of logic blocks a given task would require?

Anyone have a rough order of magnitude on what I should expect for these comon devices?:

• UART
• packet deframer with CRC32
• 8 micro core

I've seen www.opencores.org, however, they are not giving a number of gates magnitude for each project.

Answer 1

An entire Amiga can fit in 400k gates, excluding CPU. See the Minimig project, it's opensource and should include some useful reference files. There's also an FPGA 68k core somewhere online that you can check, written by tobiflex. Also check out the commodore one machine and C64/CPC cores (Z80, 6845, SID, 6502, etc) to see how they compare.

Answer 2

UART: 3200 gates. 8-bit uC: 10k gates. Check http://www.design-reuse.com/ for others.

Answer 3

I'd avoid gate counts with FPGAs, here's some 4-input look-up-table estimates (most of my experience is with Xilinx, but it'll be similar for Altera and others):

A raw UART is a few dozen LUT/FFs - if it has a bus interface to a micro, then it'll be more (likely <100 still) and if it has 16550-style FIFOs then even more (and maybe some ram blocks as well). 8-bit micro - in Xilinx, see Picoblaze (113 slices - each slice is two LUTs and two FFs, but not all of them are used in every slice)

Packet deframer - no idea - depends on the framer spec sorry :)

Answer 4

I'd recommend going to Opencores.org, finding a design similar to yours and synthesizing it. I'd say that's the most accurate way to estimate logic utilization.