vhdl

VHDL constant initialisation

Hi, I am just studying some VHDL code and for the initialisation of a constant it says the following: constant address: integer := 16#8E#; I have never seen this kind of definition before. Does anybody know how this translates to an ordinary number in decimal? Thanks! ...

Import Code from FPGA Board (Spartan 3E)

Is there any way to import code from an already programmed FPGA board, in this case, it is a Spartan 3E board. That is to say, verilog code has already been uploaded to it, so I would like a way to receive the code back in the computer since I have lost the copy. I uploaded the code with Xilinx ISE, but am not sure if it is possible to g...

Translating a VHDL monitor into a PSL assertion

Hello, I have an interesting question about PSL assertion. Here is a VHDL monitor process. It is a process dedicated to an assertion, and thus a non-synthesizable one. This monitor checks the current FSM state and stores the values of two registers: "input1" and "reg136". Finally, it triggers an "assert" statement to compare the values ...

VHDL language IDE

Possible Duplicate: Professionnal VHDL IDE ? can anybody tell me IDE where i can write VHDL codes? ...

What is ModelSim output file and how to load hex file on a ROM?

I want to simulate a microprocessor designed using VHDL in ModelSim. I wanted to know what the output file format of the simulation is? I also want to load some HEX file on the ROM of this Microporcessor...what should I do? Thanks. ...

[VHDL] Simulation not working - port mapping wrong?

VHDL code First of all, sorry for the redirect, but it's easier that way. I'm building a digital clock, but as you can see, clock_AN and clock_seg_out do not change. Is this caused by a wrong port mapping? Thanks! ...

[VHDL] how much for Sound (ADC) reading in 24khz?

Hi there, how much "sound inputs" of high fidelify (128K 44kH) may be made via ordinary FPGA (Xilinx Spartan 3, what-so-ever) without using external ADC converters (only voltage-balanced input optically taken from audio jack)? Here, http://stackoverflow.com/questions/3165266/generating-a-pure-sine-wave-as-output-form-fpga-using-vhdl-cod...

VHDL components

Hi, I've been scratching my head since my first VHDL class and decided to post my question here. Given that I have a declared entity (and also an architecture of it) and want to instantiate it inside another architecture, why is it that I seemingly have to redeclare the "entity" (component) inside this containing architecture before in...

Redundant loop inside a process (VHDL)?

Hello, I'm taking a university course to learn digital design using VHDL, and was doing some reading in the book the other day where I came across the following piece of code: architecture abstract of computer_system is ... cpu : process is variable instr_reg : word; variable PC : natural; ... begin...

Creating a VHDL backend for LLVM?

LLVM is very modular and allows you to fairly easily define new backends. However most of the documentation/tutorials on creating an LLVM backend focus on adding a new processor instruction set and registers. I'm wondering what it would take to create a VHDL backend for LLVM? Are there examples of using LLVM to go from one higher leve...

VHDL Case/When: multiple cases, single clause

Inside a process I have something like this: CASE res IS WHEN "00" => Y <= A; WHEN "01" => Y <= A; WHEN "10" => Y <= B; WHEN "11" => Y <= C; WHEN OTHERS => Y <= 'X'; END CASE; Note that case "01" and "01" get the same value. Is there correct syntax for something like WHEN "00", "01" => ? Extra note: There's far more to th...

Wrapping and switching between similar entities in VHDL

I want to describe an entity that can either function normally or be put in a test mode. The general design I have is a top level entity that wraps the "real" entity and a test entity. I am trying to figure out the best way to express this in VHDL, but I get the feeling I'm overcomplicating things. Consider a small top-level entity (re...

Simple State Machine Problem

Hi all, I have a very simple FSM which should drive some output signals of an external RAM. The problem that I have comes with handling the data bus which can be input as well as output... I am not too sure how I can handle best this case in my FSM. The problem comes from the following line: v.sram_data <= io_sram_data; Obviously...

State to std_logic

Hi all, I have defined my state as follows: type state_type is (s0, s1, s2, s3); signal state : state_type; Now I would like to use this state information to form another signal signal data : std_logic_vector(3 downto 0); signal data_plus_state : std_logic_vector(5 downto 0); .... data_plus_state <= data & state; Does anyone kn...

Reset an Altera M9K's content to 0 (power-up value)

Good day, I am working on a Stratix III FPGA which contains M9K block memories, the contents of which are conveniently initialised to zero on power-on. This suits my application very well. Is there a way to reset the contents back to zero without power-cycling/reflashing/etc the FPGA? There seems to be no such option in the megawizard ...

"Serialize" VHDL record

Suppose I have the following type definition which relies on constants to indicate vector length of the record members: type point_t is record x: std_logic_vector(X_WIDTH-1 downto 0); y: std_logic_vector(Y_WIDTH-1 downto 0); end record; I would like to convert these kind of records into std_logic_vectors to put them into, say...

Logical Operator problem VHDL

Hi, I have a very simple operator problem in VHDL. I try to compare some inputs with logical operators but get an error message... entity test is port ( paddr : in std_logic_vector(15 downto 0); psel : in std_logic; penable : in std_logic; pwrite : in std_logic ); en...

Making a 4-bit ALU from several 1-bit ALUs in VHDL

Hey, I'm trying to combine several 1 bit ALUs into a 4 bit ALU. I am confused about how to actually do this in VHDL. Here is the code for the 1bit ALU that I am using: component alu1 -- define the 1 bit alu component port(a, b: std_logic_vector(1 downto 0); m: in std_logic_vector(1 downto 0); result: out std_logic_vector(1 downto ...

Problem adding std_logic_vectors

Hi, I wanna have a simple module that adds two std_logic_vectors. However, when using the code below with the + operator it does not sythesis. library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; entity add_module is port( pr_in1 : in std_logic_vector(31 downto 0); pr_in2 : in std_logic_vector(31 d...