VHDL components

Question

Hi,

I've been scratching my head since my first VHDL class and decided to post my question here.

Given that I have a declared entity (and also an architecture of it) and want to instantiate it inside another architecture, why is it that I seemingly have to redeclare the "entity" (component) inside this containing architecture before instantiating it?

Isn't the compiler smart enough to match an instantiation to its architecture just by its name? Where is the need for the component declaration?

Thanks,

n2

Answer 1

Back when I did my VHDL assignments back when I was in school, I was required to have all our code all in one file so I don't remember whether or not you could write one file for each module and how it was done.

That being said, you would have to declare the entity you would use when defining the behavior, if you were using it much in the same way that you would define prototypes, structures, classes and whatnot in C or C++. The difference here is that you don't have the luxury of defining header files for this "redeclaration" in VHDL (at least I don't think there is an equivalent). So it seems perfectly reasonable to me to have to do this. Note that VHDL came out when C was very common and the compilers weren't "smart enough" as they are today.

A VHDL guru might have a definitive answer for this but this is how I understand it.

Answer 2

You can directly instantiate the component, if desired:

  MyInstantiatedEntity : entity work.MyEntity_E
    generic map (
        config          => whatever)
    port map (
        clk             => signal1,
        clk_vid         => signal2,
        ...

Creating a component declaration gives you the extra ability to change what gets bound to the instantiation via a configuration specification or similar.