First of all, sorry for the redirect, but it's easier that way. I'm building a digital clock, but as you can see, clock_AN and clock_seg_out do not change. Is this caused by a wrong port mapping? Thanks!
+1
A:
Your input master clock is too slow. Looking at the frequency divider cct, it looks like you've it programmed to divide a 100MHz clock. So either:
- speed up your testbench master clock
- or set the divider target to a lower number for debug purposes
Go with #2 if you want reasonable sim times!
Marty
2010-08-30 15:40:57
To what speed?Because I tried lowering it, but it didn't change a bit.
Ashwin Mertes
2010-08-30 15:57:45
Well, if you look at the code as you have it now, nothing will happen on your seconds clock until the counter in your frequency divider has hit 100 million! Try lowering the counter target number to something low like 2 or 3 for debug...
Marty
2010-08-30 16:08:27
Ok, tried that, still no result. Port mapping wrong?
Ashwin Mertes
2010-08-30 16:11:44
Marty, I changed the count range to 2, but still my AN and seg_out's would not change. My testbench is like this:reset <= '1'; wait for 5 ns; reset <= '0'; wait for 5 ns; set_time <= '1'; wait for 1 ns; set_time <= '0'; -- 40 seconden enable_min <= '0'; enable_hour <= '0'; wait for 1000 ns; enable_min <= '1'; -- 11 minuten enable_hour <= '0'; wait for 3700 ns; enable_min <= '0'; -- 21 uur enable_hour <= '1'; wait for 200 ns;I let the simulation run for about 10000 ns.
Ashwin Mertes
2010-08-30 16:16:11
Marty
2010-08-30 16:16:58
Marty,You were right! Modelsim was acting strange. I've lowered the values and now it works.Thank you!
Ashwin Mertes
2010-08-30 18:26:15