I'm trying to write a GNU make Makefile which has a load of similar targets, where the build commands vary slightly between them. I'm trying to use target-specific variables to represent these variations. Some of these variable values refer to files I want to use as prerequisites. For example:
target_1:special_filename=target1_prereq
target_2:special_filename=target2_prereq
target_1 target_2: common_filename $(special_filename)
do_something common_filename --a-weird-option=$(special_filename)
When I call 'make target_1', I want it to make target1_prereq if it doesn't exist. At the moment, it doesn't seem to use target1_prereq as a prerequisite, even though the build command (do_something) is called with the right parameter.
I'm using GNU Make 3.80.
Edit: A few more complications from the real system. Some of the variables are themselves based on the values of other variables. Manually specifying the prerequisites wouldn't scale. A slightly more complicated example:
target_1:special_filename_base=target1_prereq
target_2:special_filename_base=target2_prereq
some_filename_a = $(special_filename_base).exta
some_filename_b = $(special_filename_base).extb
target_1 target_2: common_filename $(special_filename_b) $(special_filename_a)
do_something common_filename --a-weird-option=$(special_filename_a) --second=$(special_filename_b)