The syntax you've shown is called a pattern rule in GNU make parlance, and it forms the corner stone of your solution. All you need is to add a way to get the list of .C files dynamically. Others have shown solutions that use $(shell)
to do this, but that's needlessly inefficient. I suggest you instead use $(wildcard), which is a GNU make built-in function designed for just this purpose:
SRCS = $(wildcard *.C)
OBJS = $(patsubst %.C,%.o,$(SRCS))
foo: $(OBJS)
$(CC) -o $@ $^
%.o: %.C
$(CC) $(CPFLAGS) -c $<
If you are looking for something more concise, the following will work too:
foo: $(patsubst %.C,%.o,$(wildcard *.C))
This just eliminates the variables and takes advantage of the fact that GNU make provides a default %.o: %.C
pattern rule, as well as a default rule for linking an executable together from a set of objects. Personally I would use the more verbose version as I find it easier to read and maintain, but to each their own.
Hope that helps,
Eric Melski