I have a makefile template to compile a single DLL (for a plugin system). The makefile of the user looks like this: EXTRA_SRCS=file1 file2 include makefile.in In the makefile.in I have: plugin.dll: plugin.os $(patsubst %,%.os,$(EXTRA_SRCS)) Where plugin.os is the main C++ file to be compiled. Btw, the files ending is .os are the ob...
Is there a difference between using a makefile and a Makefile? ...
"make" is not only useful for building your programming project, but it seems to be under-used in other areas. For example, many shell scripts can be rewritten as Makefiles to allow independent parts to run in parallel (with "make -jXX") to keep all your CPU cores busy, with the explicitly declared dependencies as an added benefit in ca...
Hello! I am writing a Makefile with a lot of repetitive stuff, e.g. debug_ifort_Linux: if [ $(UNAME) = Linux ]; then \ $(MAKE) FC=ifort FFLAGS=$(difort) PETSC_FFLAGS="..." \ TARGET=$@ LEXT="ifort_$(UNAME)" -e syst; \ else ...
Hello, I have a Makefile where most of my targets are created generically through a canned sequence. It seems that bash completion only suggests completions for normal targets, e.g. target_name: #$@ and not for generic targets. Is there any way to make bash completion complete all the targets, even though they are not made ex...
When i try to $ make depend -f gcc.mak a middleware on my Ubuntu machine I get this /usr/include/../include/limits.h:125:26: error: no include path in which to search for limits.h This is the contents around limits.h:125: /* Get the compiler's limits.h, which defines almost all the ISO constants. We put this #include_next outs...
I am trying to understand the difference between 'gmake' and 'make'? On my linux box they are identical: % gmake --version GNU Make 3.81 Copyright (C) 2006 Free Software Foundation, Inc. This is free software; see the source for copying conditions. There is NO warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOS...
I have the following GNU makefile: .PHONY a b c d a: b c b: d c: d d: echo HI I would like the target 'd' to be run twice -- since it is specified as a dependency by both b & c. Unfortunately, the target 'd' will be executed only once. The output of running make will simply be 'HI', instead of 'HI HI'. How can I fix this? Th...
I have a question regarding the GNU makefile example below: .PHONY: $(subdirs) build x y subdirs = a b c build: x y x: target=prepare x: $(subdirs) y: target=build y: $(subdirs) $(subdirs): $(make) -f $@/makefile $(target) When I run make, I expect make to be called for each sub-directory specifying the target 'prepare' then...
Is it possible to have a GNU makefile with a target/dependent containing a win32 path name? I'm currently using the win32 3.81 version of GNU make, and it seems to have difficulties with drive letters. For example: C:\MyTarget.obj : c:\MySource.cpp cl /c C:\MySource.cpp The above makefile snippet will generate errors. In partic...
Hello, I need to write a quick makefile for building all my projects. This is C++ code and I am using gmake. Say I have a list of directories, I want to cd to each, issue gmake command and if it succeeds, go to the next one and so on. I cooked this by looking at the gmake manual .PHONY: all clean dirs $(DIRS) dirs: $(DIRS) $(DIRS):...
Hi All, we have some C++ code that we need to create a make file in. Each .h and .C pair create an object and then some objects are linked together to form a executable. Pretty standard stuff. This non-gnu make command just builds all the files into object in a directory %.o:%.C $(CC) $(CPFLAGS) -c $< What this does is for ea...
I have a Makefile with the following type of rule: %.html: ./generate-images.py > $@ make $(patsubst %.png,%.gif,$(wildcard *.png)) The generate-images script writes not only the HTML file (to stdout) but several .png files to the current directory. The goal here is to convert them to .gif. (not really, but this is an example)...
Hi all. 1) We have a need for Makefiles to build C++ on both z/OS USS and a Linux platform. Is it advisable to use gnu make on z/OS USS in order to keep our makefiles common ? 2) If the Makefiles are common, then some steps in the Makefiles, would still be conditional to the platform. Can we do that by steps that are similar to condit...
I've a make file for a scripted system, with a lot of tests which should pass. Each test is a separate call to the scripting application: #---------------------------------------------------------------------------- # run test scripts in the module::test #---------------------------------------------------------------------------- scrip...
for example I have something like this in my makefile all: cd some_directory but when I type make I saw only 'cd some_directory' like in echo command ...
I have a makefile which has statements like below: TOPICS = dmic SRV_MODE = ifeq "$(SRV_FLAG)" "ON" SRV_MODE = 2 endif vpath d%_srv.h $(CNT_PATH) USER_PRE_TARGETS := $(foreach topic,$(TOPICS),$(topic)_srv.h) dmic_srcs = $(wildcard $(CCWSCA)/dmic/src/*.c) \ $(wildcard $(CCWSCA)/dmic/src/*.ppc) dmic_srv.h: $(dm...
I've posted the relevant bits of my makefile. When I run make all on this makefile, there's a compilation error when compiling debugosd.o. However, because make found a previously built debugosd.o, it just continues on to build dialup.otz. Without deleting all the .o's, how can I force debugosd.o to become out-of-date - and so force ma...
I'm using GNU make, and including a 3rd party library in a project that has a build system that goes berserk if CFLAGS is defined in the environment when it is called. I like to have CFLAGS defined in my environment for other reasons. The library's build is being invoked from another makefile, so that I say e.g.: 3rdparty: $(MAKE)...
Is there a way to direct make/gmake to act upon conditional dependencies? I have this rule in place: $(OBJ_DIR)/%.o: $(SRC_DIR)/%.cpp $(CPPC) -c $(FLAGS_DEV) $< -o $@ In the general case, every .cpp file has a corresponding .h file; however there are a few exceptions. Is there a way to achieve "depend on this if it exists" with gm...