gnumake

Resources for learning GNUMake?

Hi all, I'm trying to learn GNUMake for a small project I'm working on. So far, even the "basic" tutorials seem pretty rough and I've yet to make sense of the makefile syntax. Does anyone have some good resources for an absolute beginner to get familiar with GNUMake? ...

Need a makefile dependency rule that can handle missing files

We use GNU Make for our system. At the end of our makefiles, we have an include called Makedepends which generates a bunch of .d files using -MM switch on gcc. We then include the .d file for each .cc file using an include $(CXXFILES:.cc=.d) line. But when we delete file or move files, the dependancies step breaks and we have to manua...

how to have make targets for separate debug and release build directories?

Hi all, I am looking for suggestions to properly handle separate debug and release build subdirectories, in a recursive makefile system that uses the $(SUBDIRS) target as documented in the gnumake manual to apply make targets to (source code) subdirectories. Specifically, I'm interested in possible strategies to implement targets like...

mutually-exclusive job scheduling in GNU make?

Using GNU make, is it possible to create a set of targets that will never be scheduled at the same time when using the "--jobs" option? Background: To make this a little more concrete, consider a makefile of the form p1: ...deps... # no parallelization conflicts (can run at the same time as p*, e*) ...rules... p2: ...deps... ...

Why does GNU make delete a file...

I've got a slightly hackish makefile for running tests: ### Run the tests tests := tests/test1 tests/test2 ... test: $(tests) $(tests): %: %.c gcc -o $@ $(testflags) $< $@ It works, but it makes Make do something I've never seen it do before. My test is currently broken, and causes a bus error. Make gives the following outp...

What is the most reliable way of using GNUMake with filenames containing spaces?

I want to use GNUMake to run a rule-based makefile which builds a set of C files in a directory structure (on a Windows file system). The root directory, some sub-directories and some files contain spaces. Example file: "C:\Documents and Settings\<username>\My Documents\Test Dir\Build Me.c" GNUMake doesn't really work when the file pa...

Why buildtools like AutoTools?

Recently, I switched my development environment to LINUX from Windows. I have only used Visual Studio so far for C++ development. So many concepts like make, autotools are new to me. I have read GNU makefile documentation and got almost an idea about it. But I am kinda confused about autotools. AFAIK, makefiles are used to make the buil...

Portable equivalent of GNU make %-style pattern rules

I'm following the directions on the Using Check with the Autotools page in an attempt to build in support for unit test in a (currently) small C project. Although I am using Cgreen instead of Check. I'm having trouble with step 9, which is causing automake to emit a warning about the use of `%'-style pattern rules being a GNU make exten...

Automatic variables in the tests of conditionals : GNU Make

Hi, I am kind of stuck here. We have two makefiles (A requirement that I can't change) defs.mk : It contains the source file names & their extra compile flags (apart from the standard flags) e.g: C_FILES = c/src/main/rule_main.c rule_main_OPTIONAL_FLAG = +w127 rule_main_DEBUG = TRUE Makefile : It contains all the rules. Now I want t...

How to supress echos in makefile?

I have the following PHONY target in Makefile install: echo /usr/bin/shelldecrypt must be writable cp shelldecrypt /usr/bin When I run the target it displays the command it is executing prompt> make install OUTPUT IS echo /usr/bin/shelldecrypt must be writable /usr/bin/shelldecrypt must be writable c...

GNU make with many target directories

I have to integrate the generation of many HTML files in an existing Makefile. The problem is that the HTML files need to reside in many different directories. My idea is to write an implicit rule that converts the source file (*.st) to the corresponding html file %.html: %.st $(HPC) -o $@ $< and a rule that depends on all html fi...

Is it possible to implement a `trap' for GNU make

I'm wondering if there's a way to implement the similar functionality as you get in bash scripts using `trap', but for gmake, such that if the user presses CTRL-C, or if make itself fails, it can call a particular target or macro. ...

How can I configure my makefile for debug and release builds?

I have the following makefile for my project, and I'd like to configure it for release and debug builds. In my code, I have lots of #ifdef DEBUG macros in place, so it's simply a matter of setting this macro and adding the '-g3 -gdwarf2' flags to the compilers. How can I do this? EDIT: Just to clarify, when I say release/debug builds, I...

Re-execute target when specified as dependency to multiple rules

I have the following GNU makefile: .PHONY a b c d a: b c b: d c: d d: echo HI I would like the target 'd' to be run twice -- since it is specified as a dependency by both b & c. Unfortunately, the target 'd' will be executed only once. The output of running make will simply be 'HI', instead of 'HI HI'. How can I fix this? Th...

Multiple rules specify the same phony dependent, dependent only executes once

I have a question regarding the GNU makefile example below: .PHONY: $(subdirs) build x y subdirs = a b c build: x y x: target=prepare x: $(subdirs) y: target=build y: $(subdirs) $(subdirs): $(make) -f $@/makefile $(target) When I run make, I expect make to be called for each sub-directory specifying the target 'prepare' then...

Win32 paths as targets/dependencies

Is it possible to have a GNU makefile with a target/dependent containing a win32 path name? I'm currently using the win32 3.81 version of GNU make, and it seems to have difficulties with drive letters. For example: C:\MyTarget.obj : c:\MySource.cpp cl /c C:\MySource.cpp The above makefile snippet will generate errors. In partic...

Flat object file directory structure output with GNU Make

I have a C++ small project using GNU Make. I'd like to be able to turn the following source files: src/ a.cpp b/ b.cpp c/ c.cpp into the following output structure (I'm not concerned about duplicates at this point): build/ a.o b.o c.o So far I have the following, which unfortunately puts the .o and .d right next...

What does the load-average used by parallel make represent?

Using GNU make on Windows, what exactly does the load-average value represent? For example: make -j --load-average=2.5 What does the 2.5 mean? ...

Make (Parallel Jobs) on Windows

What setup works for GNU make parallel jobs (-j) on Windows? I have tried setting the shell to cmd.exe using MinGW make 3.81, this works in creating the multiple processes but make fails with the "waiting for job" message. Can this work and what is the best setup? (MinGW / Cygwin / ???) Can someone point me to a working example to test...

GNU make's -j option

Ever since I learned about -j I've used -j8 blithely. The other day I was compiling an atlas installation and the make failed. Eventually I tracked it down to things being made out of order - and it worked fine once I went back to singlethreaded make. This makes me nervous. What sort of conditions do I need to watch for when writing ...