Resources for learning GNUMake?

Question

Hi all,

I'm trying to learn GNUMake for a small project I'm working on. So far, even the "basic" tutorials seem pretty rough and I've yet to make sense of the makefile syntax.

Does anyone have some good resources for an absolute beginner to get familiar with GNUMake?

Answer 1

The definitive guide is http://www.gnu.org/software/make/manual/make.html
There is an o'reilly book "Managing Projects with GNU Make" which has more explanation. You can also uses the earlier editions, they don't cover GnuMake specifically but are a lot thinner.

Make is a dirty secret among developers - none of us understand it, we just borrow a make script from somebody else and change it. I imagine only one script was ever written from scratch (probably by the creator of the tool).

When you need to do more than the simple example most people either switch to a more modern build system like Ant or roll their own in Perl/Python/etc.

Answer 2

mgb: It's even worse that that. I once did write a complicated make system from scratch (a few thousand files, fifty or a hundred directories, four or five compilers and cross-compilation targets, 2 OS's, etc.). I sat down and learned gnu make inside and out first off, designed the system, played around with a prototype first. We were all very happy with the result.

But that was years ago. You know how I write them today? Same way you describe. It's just fiddly enough and the syntax details are obscure enough than unless you do it fairly regularly you can't remember the details. Just like any other language with non-intuitive syntax and some quirky rules, I guess.

Answer 3

The most commonly used features of make can be broken down into a couple simple concepts, targets, dependencies and variables.

Targets are the things you want to build, but the command(s) beneath a target can be compiler commands or scripts. Generally each target refers to a module in your code, but you can make these as granular as you want to suit your project.

Dependencies are files or other targets in your project. The best example of this is for a C project where you're building a binary from a bunch of object files. Each object file will need to exist before you can build the binary, so make will traverse your targets until all of the dependencies have been completed, and then run the command for the overall target.

Variables aren't always necessary, but are pretty handy for handling things like compiler flags. The canonical examples are CC and CCFLAGs which will refer to the compiler your using i.e. gcc and the flags like -ansi -Wall -o2.

A couple more general tips and tricks:

• Commands must be proceeded by a [tab] character, or they won't be executed, this is just an old relic of make, I don't recall why this is.
• By convention, you may want to include an all target to specify the default which target should be the default. This is useful when you have a complex makefile and there's a particular target you always want to be the default.
• Your makefile should be called makefile or Makefile, but if you want to call it something else, use $make -f [makefilename]
• Always use the full variable expansion syntax i.e. $(VARIABLE) or make may not output the commands you want.
• make can work recursively, so if you have a bunch of sub-modules in your project that live inside of directories, you can call make on the sub-directory makefile from within make to build each.
• If you have a really complicated project that needs an installation scripts, etc. you'll probably also want to investigate autotools which generates the makefile for you and does a bunch of tricks to check for library existence and for other portability issues.

Answer 4

I concur with the O'Reilly book suggestion.

For some helpful tips, tricks and insights into Make look at the Mr. Make articles