makefiles CFLAGS

Question

In the process of learning tinyos i have discovered that I am totally clueless about makefiles.

there are many optional compile time features that can be used by way of declaring preprocessor variables

to use them you have to do things like

CFLAGS="-DPACKET_LINK" this enables a certain feature.

and CFLAGS="-DPACKET_LINK" "-DLOW_POWER" enables two features.

can someone dissect these lines for me and tell me whats going on? Not in terms of tinyos, but in terms of makefiles!

Thanks!

Answer 1

Somewhere in the makefile the CFLAG will be used in compilation line like this:
$(CC) $(CFLAGS) $(C_INCLUDES) $<

and eventually in the execution will be translated to :

gcc -DPACKET_LINK -DLOW_POWER -c filename.c -o filename.o

This define will be passed to the source code as it was define in the header file

Answer 2

CFLAGS is a variable that is most commonly used to add arguments to the compiler. In this case, it define macros.

So the -DPACKET_LINK is the equivalent of putting #define PACKET_LINK at the top of all .c and .h files in your project. Most likely, you have code inside your project that looks if these macros are defined and does something depending on that:

#ifdef PACKET_LINK
// This code will be ignored if PACKET_LINK is not defined
do_packet_link_stuff();
#endif

#ifdef LOW_POWER
// This code will be ignored if LOW_POWER is not defined    
handle_powersaving_functions();
#endif

If you look further down in your makefile, you should see that $(CFLAGS) is probably used like:

$(CC) $(CFLAGS) ...some-more-arguments...

Answer 3

-D stands for define (in gcc) at least, which lets you #define on the command line instead of a file somewhere. A common thing to see would be -DDEBUG or -DNDEBUG which respectively activate or disable debugging code.

Answer 4

The -D option set pre-processor variables, so in your case, all code that is in the specified "#ifdef / #endif" blocks will be compiled.

I.e.

#ifdef PACKET_LINK
/* whatever code here */
#endif

The CFLAGS is a variable used in the makefile which will be expanded to it's contents when the compiler is invoked.

E.g.

gcc $(CFLAGS) source.c

Answer 5

Just for completeness in this - if you're using Microsoft's nmake utility, you might not actually see the $(CFLAGS) macro used in the makefile because nmake has some defaults for things like compiling C/C++ files. Among others, the following are pre-defined in nmake (I'm not sure if GNU Make does anything like this), so you might not see it in a working makefile on Windows:

.c.exe:
    commands:          $(CC) $(CFLAGS) $<

.c.obj:
    commands:          $(CC) $(CFLAGS) /c $<

.cpp.exe:
    commands:          $(CPP) $(CPPFLAGS) $<

.cpp.obj:
    commands:          $(CPP) $(CPPFLAGS) /c $<

Answer 6

I've found that Ask Mr. Make is a great reference for Makefile tips

http://www.cmcrossroads.com/content/category/8/147/268/