gcc dependency generation for a different output directory

Question

I'm using gcc to generate a dependency file but my build rules put the output into a subdirectory. Is there a way to tell gcc to put my subdirectory prefix in the dependency file it generates for me?

gcc $(INCLUDES) -E -MM $(CFLAGS) $(SRC) >>$(DEP)

Answer 1

If there is an argument to gcc to do this, I don't know what it is. We end up piping the dependency output through sed to rewrite all occurrences of .o as ${OBJDIR}/.o

Answer 2

Ok, just to make sure I've got the question right: I'm assuming you have test.c which includes test.h, and you want to generate subdir/test.d (while not generating subdir/test.o) where subdir/test.d contains

subdir/test.o: test.c test.h

rather than

test.o: test.c test.h

which is what you get right now. Is that right?

I was not able to come up with an easy way to do exactly what you're asking for. However, looking at http://www.gnu.org/software/gcc/news/dependencies.html, if you want to create the .d file while you generate the .o file, you can use

gcc $(INCLUDES) -MMD $(CFLAGS) $(SRC) -o $(SUBDIR)/$(OBJ)

(Given SRC=test.c, SUBDIR=subdir, and OBJ=test.o) This will create both subdir/test.o and subdir/test.d, where subdir/test.d contains the desired output as above. Hope that helps.

Answer 3

1. [GNU] make gets angry if you don't place the output in the current directory. What you really should do is run make from the build directory, and use the VPATH make variable to locate the source code. If you lie to a compiler, sooner or later it will take its revenge.

2. If you insist on generating your objects and dependencies in some other directory, you need to use the -o argument as answered by Emile.

Answer 4

The answer is in the GCC manual: use the -MT flag.

-MT target Change the target of the rule emitted by dependency generation. By default CPP takes the name of the main input file, deletes any directory components and any file suffix such as `.c', and appends the platform's usual object suffix. The result is the target.

An -MT option will set the target to be exactly the string you specify. If you want multiple targets, you can specify them as a single argument to -MT, or use multiple -MT options.

For example, -MT '$(objpfx)foo.o' might give

         $(objpfx)foo.o: foo.c

Answer 5

I'm assuming you're using GNU Make and GCC. First add a variable to hold your list of dependency files. Assuming you already have one that lists all our sources:

SRCS = \
        main.c \
        foo.c \
        stuff/bar.c

DEPS = $(SRCS:.c=.d)

Then include the generated dependencies in the makefile:

include $(DEPS)

Then add this pattern rule:

# automatically generate dependency rules

%.d : %.c
        $(CC) $(CCFLAGS) -MF"$@" -MG -MM -MP -MT"$@" -MT"$(<:.c=.o)" "$<"

# -MF  write the generated dependency rule to a file
# -MG  assume missing headers will be generated and don't stop with an error
# -MM  generate dependency rule for prerequisite, skipping system headers
# -MP  add phony target for each header to prevent errors when header is missing
# -MT  add a target to the generated dependency

"$@" is the target (the thing on the left side of the : ), "$<" is the prerequisite (the thing on the right side of the : ). The expression "$(<:.c=.o)" replaces the .c extension with .o.

The trick here is to generate the rule with two targets by adding -MT twice; this makes both the .o file and the .d file depend on the source file and its headers; that way the dependency file gets automatically regenerated whenever any of the corresponding .c or .h files are changed.

The -MG and -MP options keep make from freaking out if a header file is missing.