I have an rule that creates a directory bin: -mkdir $@ However after the first time the directory has been generated, I receive this output: mkdir bin mkdir: cannot create directory `bin': File exists make: [bin] Error 1 (ignored) Is there some way I can only run the rule if the directory doesn't exist, or suppress the output w...
Hi, Here is my makefile http://pastie.org/1104332. I am trying to compile different .c files and .s files (assembly files) from different sub directories into E:/em35x/build/mfg-sample-app-cortexm3-iar-em357-em3xx-dev0680/ then the linker should link all the .o files from the build directory (E:/em35x/build/mfg-sample-app-cortexm3-iar-e...
I am searching a make like build tool that supports (besides usual make features): Automatic deletion of temporary created files (like in GNU make for example) Regular expressions in rule patterns (like e.g. in Cook About 1: By default GNU make deletes temporary files. For example have these rules: %.c: %.y some-comand %....
Here's a skeleton Makefile just to make it easier to describe the problem: all_tests : unit_tests other_tests_1 other_tests_2 ... other_tests_N unit_tests : set1_summary.txt set2_summary.txt ... setN_summary.txt %_summary.txt : %_details.txt perl createSummary.pl --in $^ -out $@ %_details.txt : test_harness ./test_harness --t...
So I need to make sure that if I am cross-compiling for a specific target that a shell variable is set. If the variable is not set then make should display a message and then exit. I have the following rule in my makefile: .PHONY: checksource all: checksource default checksource: $(if $(and $(ifeq ($(CROSS_COMPILE), whatever)), ...
Using GNU's make, I'd like to extract the first character of a variable. Currently I'm using the shell function to have bash perform the substring. I'm wanting to know if there is a way using gmake's built-ins to do the same. DIR=/user/$(shell echo "$${USER:0:1}")/$(USER)/ ...
This is my current makefile. CXX = g++ CXXFLAGS = -Wall -O3 LDFLAGS = TARGET = testcpp SRCS = main.cpp object.cpp foo.cpp OBJS = $(SRCS:.cpp=.o) DEPS = $(SRCS:.cpp=.d) .PHONY: clean all all: $(TARGET) $(TARGET): $(OBJS) $(CXX) $(CXXFLAGS) $(LDFLAGS) $(OBJS) -o $(TARGET) .cpp.o: $(CXX) $(CXXFLAGS) -c $< -o $@ %...
In a makefile, I'd like to define a variable specifying whether the current redhat-release is greater than 5.3. (This variable will be passed to gcc as a #define) So far I've come up with: # Find out which version of Red-Hat we're running RH_VER_NUM = $(shell /bin/grep -o [0-9].[0-9] /etc/redhat-release) RH_GT_5_3 = $RH_VER_NUM > '5.3'...
I want to write something like regex: SRC:="a.dat.1 a.dat.2" $(SRC): %.dat.%: (\\1).rlt.(\\2) dat2rlt $^ $@ so that a.dat.1 and a.dat.2 will give a.rlt.1 and a.rlt.2. In GNU Make info page, it says "the % can be used only once". Is there some trick to achieve this in GNU Make? ...
Hi Today when I play with Qt I use qmake to generate the Makefile, and that works quite well. However sometimes I want to add more stuff to the generated Makefile, without having to edit the generated Makefile. Let's say that we beside the source code have a Doxygen directory, and there I need to run some doxygen commands to gener...
I'm trying to create a Makefile that will download and process file a file to generate targets, this is a simplified version: default: all .PHONY: all clean filelist.d clean: @rm -fv *.date *.d #The actual list comes from a FTP file, but let's simplify things a bit filelist.d: @echo "Getting updated filelist..." @echo "LIST...
CC = g++ CFLAGS = -Wall RM = /bin/rm -rf BIN_DIR = ifeq "$(DEBUG)" "1" BIN_DIR = Debug else BIN_DIR = Release endif OBJS = \ $(BIN_DIR)/Unit.o $(BIN_DIR)/%.o: src/%.c @echo Building "$@" @g++ -c "$<" -o"$@" all: $(OBJS) clean: $(RM) $(BIN_DIR) .PHONY: all clean However, when I try to build my project this, it gives m...
I have some makefile: $(PROGRAM_NAME): index.o @echo "linking" @echo $(index_o) //linking export index_o:=. index.o: $(MAKE) -C some_dir index.o at some_dir makefile export index_o:=$(index_o)/index.o index.o: @echo "compiling" @echo $(index_o) //compiling output: compiling ./index.o linking . need ou...
I have some static library. for example libpuchuu.a it depends on dynamic library. for example libSDL.so (but of cource I have libSDL.a) Creation of libpuchuu.a is simple: ar -rcs object_file_1.o object_file_2.o But I can't link my project with libpuchuu.a! undefined references attack my console! At some forum I have found such sente...
I understand that the fastest and the most lightweight binary at windows generate only msvc compiler Express edition of msvc is free http://www.microsoft.com/express/windows/ but how to use cl.exe instead of g++.exe? is it possible in common by using GNU make variables produce makefiles which will works with cl.exe and g++? for examp...
A long time ago, I remember using some Solaris make, and they had an ingenious option that would automatically detect when the compiler options had changed, and rebuild all rules appropriately. For example, suppose I switch from: g++ -O3 to g++ -g Then all files should be recompiled. I'm using gnu make, and haven't found any featu...
I'm working on a medium sized project which contains several libraries with interdependence's which I've recently converted over to build using a non-recursive makefile. My next goal is to enable building of both debug and release builds out of the same source tree at the same time (make debug;make release). My first step was to make d...
I had a simple variable definition in my makefile: THIS := ~/edan and it had trailing spaces in the line. Later, when I defined another variable in terms of this one: WARES := $(THIS)/wares the actual variable defined was /home/directory/edan wares and then the make clean rule removed /home/directory/edan instead...