Exiting from a make file if the state of two shell variables are a certain state

Question

So I need to make sure that if I am cross-compiling for a specific target that a shell variable is set. If the variable is not set then make should display a message and then exit.

I have the following rule in my makefile:

.PHONY: checksource

all: checksource default

checksource:
    $(if $(and $(ifeq ($(CROSS_COMPILE), whatever)), $(ifeq ($(VARIABLE),))), \
    ($(shell echo "Error! VARIABLE not defined!") \
     $(shell exit 2)))

If $CROSS_COMPILE is set to whatever:

$> echo $CROSS_COMPILE
whatever
$>

and $VARIABLE is not defined:

$> echo $VARIABLE

$>

It does not exit the make and the default target is built. Okay I know that I could just use nested ifeq to do this but I want to make it pretty (and learn a bit more about makefiles).

Help!

advTHANKSance

M

Answer 1

There is no such thing as $(ifeq). I still think you should do the check in the makefile itself, not as one of the targets:

ifeq ($(CROSS_COMPILE),whatever)
ifeq ($(VARIABLE),)
$(error Variables not set correctly.)
endif
endif

And if you're set on avoiding nested ifeq:

ifeq ($(or $(subst whatever,,$(CROSS_COMPILE)),$(VARIABLE)),)
$(error Variables not set correctly.)
endif

But I fail to see how that's an improvement. If you want to do it in a target, just use the shell and don't bother with make functions:

checksource:
    @if [ "$(CROSS_COMPILE)" = whatever -a -z "$(VARIABLE)" ]; then \
        echo "Error: Variables not set correctly"; exit 2; \
    else true; fi

I'd still go with the first option, because you can stop make before it stat s all the files names in Makefile and decides to start executing checksource.

Answer 2

Doing it in make is always better than using the shell (whether via $(shell) or a recipe). If you do do the check in a recipe, then it means that the Makefile can contain other targets that do not need this particular assert.

assert = $(if $(filter whatever,${CROSS_COMPILE}),$(if ${VARIABLE},,$(error Urk! Variable problem)))

checksource:
        ${assert}some shell commands...

P.S. If you ran your original make with --warn-undefined-variables you may have got some clue why your macros were not expanding properly:

$ make -f 1.mak CROSS_COMPILE=whatever --warn-undefined-variables
1.mak:6: warning: undefined variable `ifeq (whatever, whatever)'
make: *** No rule to make target `default', needed by `all'.  Stop.