GNU make scope of variable

Question

I have some makefile:

$(PROGRAM_NAME): index.o
    @echo "linking"
    @echo $(index_o)
    //linking

export index_o:=.
index.o:
    $(MAKE) -C some_dir index.o

at some_dir makefile

export index_o:=$(index_o)/index.o
index.o:
    @echo "compiling"
    @echo $(index_o)
    //compiling

output:

compiling ./index.o linking .

need output:

compiling ./index.o linking ./index.o

How to share changes of variable to the parent make thread? May be I need real global variable... I have read http://www.gnu.org/software/automake/manual/make/Recursion.html but not found

Answer 1

You can't push variable back to parent processes.

You may be interested in reading Recursive Make Considered Harmful. Short-short version: recursion isn't necessary for controlling large builds and causes trouble.