how do wild character % work in makefile rules

Question

I have a makefile.

I need to build a set of targets under C:/bin/ from the source files under src1 and src2.

let them be required in the order say

${DEST_DIR}/a.o ${DEST_DIR}/b.o ${DEST_DIR}/c.o ${DEST_DIR}/d.o

in some part of makefile

DEST_DIR = C:/bin

SRC_DIR1 = C:/src1

SRC_DIR2 = C:/src2

and i've the rules for them as follows

#rule#1

${DEST_DIR}/%.o : ${SRC_DIR1}/%.c

  #the command required to build the target
  echo "Source: $< Target: $@ "

#rule#2

${DEST_DIR}/%.o : ${SRC_DIR2}/%.c

  #the command required to build the target
  echo "Source: $< Target: $@ "

Let a.c and b.c are in SRC_DIR1 and c.c and d.c are in SRC_DIR2

When i build it builds fine going to rule#1 for a.o and b.o, then rule#2 for c.o and d.o

Now my question is I dint expect it'd be fine. coz i was expecting it to go for rule#1 for c.o and throw an error saying "no rule to make target c.c". But it goes for rule#2 and builds c.o from c.c in SRC_DIR2.

So can someone explain me how it works? How the wild card character % works in this case and how rule matching occurs.

Im a beginner. Just learnt what a makefile is, a week back.. :)

Answer 1

Make will not allow two sets of commands for, say, a.o, but it will allow overlapping pattern rules even if the target pattern is exactly the same.

When you ask for c.o, since there is no specific rule for "c.o", make looks through the pattern rules for a match. From the GNU make manual: "In order for the pattern rule to apply, its target pattern must match the file name under consideration and all of its prerequisites (after pattern substitution) must name files that exist or can be made." So the first rule doesn't apply, and make moves on to the second, which does.