I am self studying computer architecture offer at Michigan university. I do not understand why the memory layout for d . ( http://www.flickr.com/photos/45412920@N03/4442695706/ ) Maybe I did not understanding the here( http://www.flickr.com/photos/45412920@N03/4441916461/sizes/l/ ) well.
The second link shows that MIPS cannot pack variables, therefore the addresses they take up must fall on word boundaries.
if short is half word aligned, it takes up two bytes, int, is word aligned so it takes up 4 bytes, double must be doubleword aligned so it takes up 8 bytes.
In order to align at these places..
A zero in the Least Significant bit (LSB) would indicate every other or every 2 bytes (half word aligned), 2 Zeros indicates every 4th byte, and 3 zeros every 8th byte.
Address (4 LSBs)
XXX0 - half word aligned (2 bytes)
XX00 - Word aligned (4 bytes)
X000 - Double word aligned (8 bytes)
The double must be double word aligned so it can not start at 308 (100110100) because it is only word aligned (2 LSBs = 0) it must start at the next double word alignment 312 (100111000)
[Addr] [Binary] [Alignment]
300 100101100 Word, Half-Word
301 100101101
302 100101110 Half-Word
303 100101111
304 100110000 Double-Word, Word, Half-Word
305 100110001
306 100110010 Half-Word
307 100110011
308 100110100 Word, Half-Word
309 100110101
310 100110110 Half-Word
311 100110111
312 100111000 Double-Word, Word, Half-Word
Memory access on the MIPS is word aligned which means that is reads the memory 32 bits/4 bytes at a time. Since variable "b" is a single byte, it actually reads addresses 300-303. If variable "c" were to start at 301, the processor would have to know that "b" is only a byte and zero out the other bytes and possibly shift it to the LSB position (or the compiler would have to do it). Either way, it's more efficient to just alight all memory access on 4 byte boundaries (multiple of 4).
See Data Structure Alignment for more info.