Makefile automatic link dependency ?

Question

It's easy to let program figure out the dependency at compile time, (with gcc -MM). Nevertheless, link dependency (deciding which libraries should be linked to) seems to be difficult to figure out. This issue become emergent when multiple targets with individual libraries to link to are needed.

For instance, three dynamic library targets t1.so, t2.so and t3.so needs to be built. t1.so needs math library (-lm), while t2 and t3 don't. It would be tedious to write separate rules. A single rule requiring the three targets linked with math library saves the trouble. However, it causes inflation of target size since math library is unused for t2.so and t3.so.

Any ideas?

Answer 1

This is not as easy to figure out as finding needed headers. gcc -MM is just some fancy way to use the preprocessor, but it knows pretty much nothing about the way the code is used or works: you could include some headers full of #define's or introduce complex dependencies library dependencies.

I would stick with writing explicit linking dependencies for all targets (3 in your case). You can collect common dependencies in LDFLAGS.