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Where in the Fetch-Execute cycle is a value via an address mode decoded

I'm currently building a small CPU interpreter that has support several addressing modes, including register-deferred and displacement. It utilizes the classic IF-ID-EX-MEM-WB RISC-pipeline. In what stage of the pipeline is the value for an address-moded operand decoded. For example:

addw r9, (r2), 8(r3)

In what stage is (r2) and 8(r3) would be decoded into their actual values?

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