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625

answers:

3
LEA EAX, [EAX]

I encountered this instruction in a binary compiled with the Microsoft C compiler. It clearly can't change the value of EAX. Then why is it there at all?

+1  A: 
LEA EAX, [EAX]

Indeed doesn't change the value of EAX. As far as I understand, it's identical in function to:

MOV EAX, EAX

Did you see it in optimized code, or unoptimized code?

Eli Bendersky
It's optimized code alright. But how does that justify/explain this LEA?
Frederick
@Frederick: had it not been optimized, I guess it would make sense if the compiler uses LEA for some sort of computation and a special case generated this redundant statement (this happens in unoptimized code)
Eli Bendersky
This is a binary released to customers by my company. So it has to be the optimized version.
Frederick
"So it has to be the optimized version". Not necessarily. What if they forgot to turn on `/O2`?
Alex
the LEA instruction could be execute faster on a Pentium 4 than a MOV instruction(and calculations are still today fast using LEA) so i would point this as a reason for LEA.
Quonux
+36  A: 

It is a NOP.

The following are typcially used as NOP. They all do the same thing but they result in machine code of different length. Depending on the alignment requirement one of them is chosen:

xchg eax, eax         = 90
mov eax, eax          = 89 C0 
lea eax, [eax + 0x00] = 8D 40 00 
codaddict
Thanks unicornaddict. That clears it up.
Frederick
++ this makes sense
Eli Bendersky
Actually, it's not strictly a `NOP`, because it introduces a data dependency on `EAX`. Modern CPUs detect this specific pattern as a `NOP` and ignore the data dependency, but some older CPUs might not.
Jörg W Mittag
Actually, the opcode for `nop` is `0x90`, which is the same as `xchg eax, eax`
Nathan Fellman
well, it is wrong that "modern cpu's detect this specific pattern as a NOP", they still introduce _false_ data dependency chains. There are only some true NOP's out there where the decoders just don't introduce any data-dependencys.
Quonux
+17  A: 

From this article:

This trick is used by MSVC++ compiler to emit the NOP instructions of different length (for padding before jump targets). For example, MSVC++ generates the following code if it needs 4-byte and 6-byte padding:

8d6424 00 lea [ebx+00],ebx ; 4-byte padding 8d9b 00000000
lea [esp+00000000],esp ; 6-byte padding

The first line is marked as "npad 4" in assembly listings generated by the compiler, and the second is "npad 6". The registers (ebx, esp) can be chosen from the rarely used ones to avoid false dependencies in the code.

So this is just a kind of NOP, appearing right before targets of jmp instructions in order to align them.

Interestingly, you can identify the compiler from the characteristic nature of such instructions.

Frederick
Saying it's a `NOP` is only half the answer (yet, oddly, the selected one). Explaining why you'd want to do these `NOP`s is the complete answer. Well done.
JUST MY correct OPINION